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Figure 10.

PXIe-6569 with 64 LVDS Out, Rows D-C

Connector Signal

FPGA Signal

GND

GND
SE 6
SE_GND_TERM

SE 7
SE_GND_TERM

DO 21+
DO 21-
GND
DO 22+
DO 22-
GND
DO 23+
DO 23-
GND
DO 24+
DO 24-
GND
DO 25+
DO 25-
GND
DO 26+
DO 26-
GND
DO 27+
DO 27-
GND
DO 28+
DO 28-
GND
DO 29+
DO 29-
GND
DO 30+
DO 30-
GND
DO 31+
DO 31-
GND

GND

D1
D2
D3

D5
D6

D8
D9

D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39

D40

Connector Signal

FPGA Signal

aSeGpio(5)

aSeGpio(7)

aDiﬀGpio_p(0)
aDiﬀGpio_n(0)

aDiﬀGpio_p(1)
aDiﬀGpio_n(1)

aDiﬀGpio_p(3)
aDiﬀGpio_n(3)

aDiﬀGpio_p(5)
aDiﬀGpio_n(5)

aDiﬀGpio_p(9)
aDiﬀGpio_n(9)

aDiﬀGpio_p(7)
aDiﬀGpio_n(7)

aDiﬀGpio_p(2)
aDiﬀGpio_n(2)

aDiﬀGpio_p(10)
aDiﬀGpio_n(10)

aDiﬀGpio_p(15)
aDiﬀGpio_n(15)

aDiﬀGpio_p(13)
aDiﬀGpio_n(13)

aDiﬀGpio_p(6)
aDiﬀGpio_n(6)

C2
C3

C5
C6

C8
C9

C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40

Bank

aSeGpio(13)

aSeGpio(15)

aDiﬀGpio_p(4)
aDiﬀGpio_n(4)

aDiﬀGpio_p(8)
aDiﬀGpio_n(8)

aDiﬀGpio_p(12)
aDiﬀGpio_n(12)

aDiﬀGpio_p(11)
aDiﬀGpio_n(11)

aDiﬀGpio_p(16)
aDiﬀGpio_n(16)

aDiﬀGpio_p(14)
aDiﬀGpio_n(14)

aDiﬀGpio_p(19)
aDiﬀGpio_n(19)

aDiﬀGpio_p(17)
aDiﬀGpio_n(17)

aDiﬀGpio_p(21)
aDiﬀGpio_n(21)

aDiﬀGpio_p(20)
aDiﬀGpio_n(20)

aDiﬀGpio_p(18)
aDiﬀGpio_n(18)

GND

SE 2

SE_GND_TERM

SE 3

SE_GND_TERM

DO 32+

DO 32-

GND

DO 33+

DO 33-

GND

DO 34+

DO 34-

GND

DO 35+

DO 35-

GND

DO 36+

DO 36-

GND

DO 37+

DO 37-

GND

DO 38+

DO 38-

GND

DO 39+

DO 39-

GND

DO 40+

DO 40-

GND

DO 41+

DO 41-

GND

DO 42+

DO 42-

GND

ni.com

PXIe-6569 Getting Started Guide

Содержание PXIe-6569

Страница 1: ...PXIe 6569 Getting Started Guide 2023 09 11...

Страница 2: ...Contents Getting Started Guide 3 ni com 2 PXIe 6569 Getting Started Guide...

Страница 3: ...odules are not installable or interchangeable on the PXIe 6569 device The PXIe 6569 is available in the following fixed LVDS configurations PXIe 6569 with 32 LVDS In 32 LVDS Out PXIe 6569 with 64 LVDS...

Страница 4: ...e information Environmental information LabVIEW FPGA Module Help Basic functionality of the FPGA module Instructions for developing and debugging custom hardware logic FlexRIO 21 7 Readme Minimum syst...

Страница 5: ...of damage Notice Never touch the exposed pins of connectors Note Do not install a module if it appears damaged in any way 3 Unpack any other items and documentation from the kit Store the module in th...

Страница 6: ...dle the installation Refer to the NI Package Manager Manual for more information about installing removing and upgrading NI software using NI Package Manager 3 Follow the instructions in the installat...

Страница 7: ...he rear of the chassis making sure that the injector ejector handle is pushed down as shown in the following figure 4 When you begin to feel resistance push up on the injector ejector handle to fully...

Страница 8: ...11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F7 D4 D1 D2 D3 D5 D6 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D2...

Страница 9: ...Gpio_p 57 aDi Gpio_n 57 aDi Gpio_p 60 aDi Gpio_n 60 aDi Gpio_p 62 aDi Gpio_n 62 aDi Gpio_p 68 aDi Gpio_n 68 E4 E1 E2 E3 E5 E6 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26...

Страница 10: ...i Gpio_n 2 aDi Gpio_p 10 aDi Gpio_n 10 aDi Gpio_p 15 aDi Gpio_n 15 aDi Gpio_p 13 aDi Gpio_n 13 aDi Gpio_p 6 aDi Gpio_n 6 GND GND SE 2 SE_GND_TERM SE 3 SE_GND_TERM DI 21 DI 21 GND DI 22 DI 22 GND DI 23...

Страница 11: ...B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B7 B40 aSeGpio 9 From clocking circuitry aDi Gpio_p 28 aDi Gpio_n 28 aDi Gpio_p 23 aDi Gpio_n 23 aDi Gpio_p 29 aDi Gpio...

Страница 12: ...aDi Gpio_n 57 aDi Gpio_p 60 aDi Gpio_n 60 aDi Gpio_p 62 aDi Gpio_n 62 aDi Gpio_p 68 aDi Gpio_n 68 E4 E1 E2 E3 E5 E6 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E...

Страница 13: ...D GND SE 6 SE_GND_TERM SE 7 SE_GND_TERM DI 21 DI 21 GND DI 22 DI 22 GND DI 23 DI 23 GND DI 24 DI 24 GND DI 25 DI 25 GND DI 26 DI 26 GND DI 27 DI 27 GND DI 28 DI 28 GND DI 29 DI 29 GND DI 30 DI 30 GND...

Страница 14: ...i Gpio_n 27 aDi Gpio_p 31 aDi Gpio_n 31 aDi Gpio_p 32 aDi Gpio_n 32 aDi Gpio_p 40 aDi Gpio_n 40 aDi Gpio_p 36 aDi Gpio_n 36 aDi Gpio_p 45 aDi Gpio_n 45 aDi Gpio_p 39 aDi Gpio_n 39 Connector Signal FPG...

Страница 15: ...pio_n 57 aDi Gpio_p 60 aDi Gpio_n 60 aDi Gpio_p 62 aDi Gpio_n 62 aDi Gpio_p 68 aDi Gpio_n 68 E4 E1 E2 E3 E5 E6 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30...

Страница 16: ...o_n 2 aDi Gpio_p 10 aDi Gpio_n 10 aDi Gpio_p 15 aDi Gpio_n 15 aDi Gpio_p 13 aDi Gpio_n 13 aDi Gpio_p 6 aDi Gpio_n 6 C4 C1 C2 C3 C5 C6 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24...

Страница 17: ...0 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A7 Bank 44 Bank 44 GND GND SE 5 SE_GND_TERM DO 10 DO 10 DO 11 DO 11 GND DO 12 DO 12 GND DO 13 DO 13 GND DO 14 DO 14 GN...

Страница 18: ...rminated on the user side of the SEARAY cable through a 56 10 resistor to GND If the user side termination is not possible leave it disconnected CLKIN CLKOUT Clock Terminals for clocking inputs and ou...

Страница 19: ...in the configuration tree and clicking Self Test in the MAX toolbar MAX self test performs a basic verification of hardware resources Accessing FlexRIO with Integrated I O Examples The FlexRIO driver...

Страница 20: ...le names and descriptions demonstrate how the examples would be displayed to a user whose module includes a 32 LVDS In 32 LVDS Out variation and a KU035 FPGA PXIe 6569 32 In 32 Out KU035 Basic Interfa...

Страница 21: ...esign in the Vivado ADE Read Write Calibration Data vi Demonstrates how to read and write calibration data and metadata into the storage space of FlexRIO with Integrated I O devices FPGA Carrier Block...

Страница 22: ...t two types of CLIP user defined and socketed User defined CLIP allows you to insert HDL IP into an FPGA target enabling VHDL code to communicate directly with an FPGA VI Socketed CLIP provides the sa...

Страница 23: ...lean data type and the single ended PFI lines using another boolean data type Generation channels are clocked by a single generation clock signal and acquisition channels are clocked by a single acqui...

Страница 24: ...LVDS Out Refer to Front Panel and Connectors for PXIe 6569 connector signals and the associated FPGA signal information PXIe 6569 Basic Socketed CLIP Signals CLIP Signal Name Direction Data Type Desc...

Страница 25: ...VDS_PFI_Rd From CLIP Boolean LVDS_PFI_Wr To CLIP Boolean LVDS_Data_Wr To CLIP U32 HIHO U64 All Out Provides read write access to all LVDS channels The least significant bit LSB of the U32 HIHO U64 All...

Страница 26: ...MK04832 onboard clocking ICs Refer to Figure 1 Figure 3 and Figure 5 for additional information TX RX Delay Adjust Steps To CLIP U16 Sets the number of delay steps to apply to the corresponding TX RX...

Страница 27: ...djust Strobe is asserted TX RX Delay Adjust Strobe To CLIP Boolean Applies the delay to the digital line TX RX Delay Adjust Steps and TX RX Delay Increment should be configured before asserting the TX...

Страница 28: ...o 511 delay taps as the upper limit Refer to the UG571 Ultrascale Architecture SelectIO Resources user guide at www xilinx com for additional information on the Align_Delay tap value The PXIe 6569 CLI...

Страница 29: ...I32 Returns IO module errors to be reported by the driver SE_Data_Output_Enab le To CLIP Boolean Provides read write access to all single ended channels SE_Data_Output_Enab le values 1 Use SE_Data_Wr...

Страница 30: ...he generated clocks are output on DO 13 HIHO and All Out DO 29 All Out and DO 54 All Out Clk Out Inversion DO54 All Out To CLIP Boolean Clk Out Inversion DO29 All Out To CLIP Boolean Clk Out Inversion...

Страница 31: ...ing TX RX data line This delay is applied after the corresponding TX RX Delay Adjust Strobe is asserted The delay can only be adjusted within the allowable delay limits of the FPGA Adjusting outside t...

Страница 32: ...d TX RX Delay Increment should be configured before asserting the TX RX Delay Adjust Strobe signal After asserting this strobe signal wait until TX RX Delay Done has asserted before asserting TX RX De...

Страница 33: ...y tap value The PXIe 6569 CLIP enforces the upper delay limit by preventing any further delay increments when the 511 tap delay value is reached The PXIe 6569 CLIP also enforces the lower delay limit...

Страница 34: ...lection 6569 Configure TX Clocks RX Clk Selection 6569 Configure RX Clocks RxDataClk To LabVIEW Configure Reference Clock Figure 13 All In Clock Diagram for SERDES CLIP RxSSClk Bank 44 DI0 FPGA RxData...

Страница 35: ...e 16 HIHO Clock Diagram for Basic CLIP LMK MUX MUX InternalClk ExtClkIn LMK Si514 SampleClk DeviceClk RxSSClk DI13 FPGA TX Clk Selection 6569 Configure TX Clocks RX Clk Selection 6569 Configure RX Clo...

Страница 36: ...about NI service offerings such as calibration options repair and replacement Visit ni com register to register your NI product Product registration facilitates technical support and ensures that you...

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