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National Instruments Corporation
9
18-Slot NI PXIe-1065 Backplane Installation Guide
Figure 4.
Distribution of PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100
PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 have the default timing
relationship described in Figure 5.
Figure 5.
System Reference Clock Default Behavior
To synchronize the system to an external clock, you can drive PXI_CLK10
from an external source through the PXI_CLK10_IN pin on the system
timing slot. Refer to Table 11,
XP4 Connector Pinout for the System Timing
Slot
, for the pinout. When a 10 MHz clock is detected on this pin, the
backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 signals to this external clock and distributes these signals
to the slots. (Refer to Figure 4 for the distribution of PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100.) Refer to
Backplane Specifications
for the specification information for an external clock provided on the
PXI_CLK10_IN pin of the system timing slot.
P2
P1
XP4
XP3
TP2
TP1
P2
P1
P2
P1
P2
P1
P1
P1
P1
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
XP4
XP3
XP2
XP1
P1
10 MHz
REF IN
10 MHz
REF OUT
PXI_CLK10_IN
1
8
9
10
PXIe_CLK100
PXIe_SYNC100
PXI_CLK10
7
H
11
H
H
12
H
13
14
15
6
5
4
3
2
16
17
18
PXIe_CLK100
PXI_CLK10
PXIe_SYNC100
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
