18-Slot NI PXIe-1065 Backplane Installation Guide
18
ni.com
Backplane bare-board material ...............UL 94 V-0 Recognized
Backplane connectors .............................Conforms to IEC 917 and
IEC 1076-4-101, and are
UL 94 V-0 rated
System Synchronization Clock (PXI_CLK10, PXIe_CLK100,
PXIe_SYNC100) Specifications
10 MHz System Reference Clock: PXI_CLK10
Maximum slot-to-slot skew ....................1 ns
Accuracy .................................................±25 ppm max. (guaranteed over
the operating temperature range)
Maximum jitter .......................................5 ps RMS phase-jitter
(10 Hz–1 MHz range)
Duty-factor..............................................45%–55%
Unloaded signal swing............................3.3 V ±0.3 V
Note
For other specifications, refer to the
PXI-1 Hardware Specification
.
100 MHz System Reference Clock: PXIe_CLK100 and
PXIe_SYNC100
Maximum slot-to-slot skew ....................100 ps
Accuracy .................................................±25 ppm max. (guaranteed over
the operating temperature range)
Maximum jitter .......................................3 ps RMS phase-jitter
(10 Hz–12 kHz range)
2 ps RMS phase-jitter
(12 kHz–20 MHz range)
Duty-factor for PXIe_CLK100...............45%–55%
Absolute single-ended voltage swing
(When each line in the differential pair
has 50
Ω
termination to 1.30 V
or Thévenin equivalent)..........................400–1000 mV
Note
For other specifications, refer to the
PXI-5 PXI Express Hardware Specification
.
