Chapter 2 Register Map and Descriptions
Static DIO Register-Level Programmer Manual
2-24
ni.com
RTSI Pulse when Edge Detected
This register configures which RTSI lines to pulse for 200 ns when there is an edge detected
on any of the lines configured for monitoring.
Address Offset:
0x0E
Type:
Read-write
Size:
16-bit
Bit Map:
Bit
Name
Description
15–9
Reserved
Write only zeros to these bits.
8–0
RTSI PED(<8..0>)
If a bit is 1 in this register, it should not be 1 in
any other RTSI register. Write a 1 to a bit to
make that RTSI line drive the value of the
corresponding pin of the RTSI-enabled input
port. RTSI PED(8) corresponds to the PXI Star
Trigger line on PXI devices.
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RTSI
PED(8)
7
6
5
4
3
2
1
0
RTSI
PED(7)
RTSI
PED(6)
RTSI
PED(5)
RTSI
PED(4)
RTSI
PED(3)
RTSI
PED(2)
RTSI
PED(1)
RTSI
PED(0)
Содержание PCI-6528
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