devices are ±180 degrees out of phase. If the devices are zero degrees out of phase, device
alignment offset is also zero degrees.
Note
For the best synchronization results, minimize the phase offset between
devices.
Caution
Before attempting to synchronize your NI FlexRIO devices, notice the
following caveats:
•
Synchronization does not account for differences in analog signal paths.
•
Synchronization does not account for data pipeline delays that occur before and after the
synchronization VIs. For example, synchronization does not account for ADC/DAC
pipeline delays.
•
The synchronized edge is always delayed relative to the unsynchronized edge. The
application is responsible for accounting for this delay, if necessary. The synchronization
VIs provide the actual synchronization delay value.
•
Lock all devices to a common time reference. Use the Reference Clock as the time
reference.
•
Set the synchronization registers for the Reference Clock to zero.
•
Synchronization does not account for propagation delays of the Reference Clock.
•
All Sample Clocks must have a fixed phase relationship with each other.
•
The Common Periodic Time Reference (CPTR) period must be greater than the
maximum propagation delay of a signal from the master device to any slave device across
the selected FPGA I/O line.
•
The CPTR period must be the same across all devices. Devices can have different Sample
Clock frequencies if the device Sample Clocks have a fixed phase relationship.
•
Route the FPGA I/O lines to all the devices that you are synchronizing.
Synchronization Versions
The synchronization library provides two alignment methods depending on user needs: FPGA
self-synchronization and host-driven synchronization. Both synchronization methods produce
the same quality of synchronization, but differ in their requirements and versatility of
operation.
FPGA Self-Synchronization
FPGA self-synchronization does not require host involvement. Using the host VIs is optional.
The FPGAs can all independently align their CPTRs. To perform a self-synchronization, your
devices must meet the following requirements:
•
Sample Clocks are locked to the same Reference Clock.
•
Sample Clocks are an integer multiple of the Reference Clock.
•
All the devices are fewer than 90 degrees out-of-phase with each other.
Note
FPGA self-synchronization is repeatable only if the devices meet all the
requirements. If the devices do not meet the requirements, use host-driven
synchronization.
18 | NI 5791R User Manual and Specifications | ni.com
