The NI-579x Configuration Design Library host VIs all require a register bus object for the
device you want to configure. Create the register bus object using Open Session.vi, or use
ni579x Open.vi.
For more information about how to use the NI-579x Configuration Design Library, refer to the
example located at
<labview>\examples\instr\ni579x\Streaming
\Streaming.lvproj
.
FPGA VI Requirements
Copy all the controls, indicators, and FPGA logic required to use the NI-579x Configuration
Design Library from the following VI:
<labview>\instr.lib\ni579x\Config
\v1\FPGA\Public\ni579x Config FPGA Template.vi
. The FAM Support installer
installs this VI on your system.
Configure your FPGA target to contain a FIFO with the following configuration.
•
Name:
reg.host instruction fifo 0
•
Type: Host to Target - DMA
•
Requested number of elements: 1,023
•
Data type: U64
•
Arbitration for read: Arbitrate if multiple requestors only
•
Number of elements per read: 1
Host VI Requirements
Configure your host VI to use the NI-579x Configuration Design Library using the following
configuration:
1.
Create a Register Bus object for your device and initialize the session using ni579x
Open.vi.
2.
Use any of the NI-579x Configuration Design Library Host VIs using the Register Bus
object returned by the ni579x Open VI.
3.
To access the Host VIs, select
Functions
»
Instrument I/O
»
Instrument Drivers
»
NI-579x Configuration
.
4.
Close the session using the ni579x Close VI.
Synchronization Overview
Synchronization coordinates Sample Clock cycles across multiple NI FlexRIO devices.
Sources of error, such as common clock propagation delay, cabling and cable lengths, analog
delays in the FPGA module and/or adapter module, and skew/jitter in the common clock, can
affect frequency and phase relationships between devices.
Use the programming example to synchronize across multiple NI FlexRIO adapter modules.
Synchronization aligns the devices so that the devices are synchronized to the nearest Sample
Clock cycle. The devices may be offset by up to one half of one Sample Clock cycle, if the
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