background image

Using Your NI 5772R with a LabVIEW FPGA
Example VI

Note

 

You must install the software before running this example. Refer to the

NI FlexRIO FPGA Installation Guide and Specifications

 for more information about

installing your software.

The NI FlexRIO Adapter Module Support software includes an example project to help you
get started creating your LabVIEW FPGA application. This section explains how to use an
existing LabVIEW FPGA example project to generate and acquire samples with the NI 5772R.
This example requires at least one SMA cable for connecting signals to your NI 5772R.

Note

 

The examples available for your device are dependent on the version of the

software and driver you are using. For more information about which software
versions are compatible with your device, visit 

ni.com/info

, enter

rdsoftwareversion

 in the text field, and click the NI FlexRIO link in the results.

The NI 5772R example project includes the following components:

A LabVIEW FPGA VI that you can compile and run on the FPGA embedded in the
hardware

At least one VI that runs on Windows and interacts with the LabVIEW FPGA VI

Note

 

In the LabVIEW FPGA Module software, NI FlexRIO adapter modules are

referred to as 

IO Modules

.

Related Information

Block Diagrams

 on page 8

FPGA Example VI Steps

1. Connect one end of an SMA cable to AI 0 on the NI 5772 front panel and the other end of

the cable to your device under test (DUT).

2. Launch LabVIEW.
3. Click 

Help

»

Find Examples

 to launch the NI Example Finder.

4. In the 

NI Example Finder

 window, select 

Hardware Input and Output»FlexRIO»IO

Modules»NI 5772

.

5. Select 

NI 5772 - Getting Started.lvproj

.

6. In the 

Project Explorer

 window, open 

NI 5772 - Getting Started (Host).vi

 under 

My

Computer

 to open the host VI. The Open FPGA VI Reference function in this VI uses

the NI PXI-7952R as the FPGA target by default. If you are using an NI FlexRIO FPGA

module other than the NI PXI-7952R, complete the following steps to change to the

FPGA VI to support your target.
a) Select 

Window»Show Block Diagram

 to open the VI block diagram.

b) On the block diagram, right-click the Open FPGA VI Reference (PXI-7952R)

function and select 

Configure Open FPGA VI Reference

.

12 | 

NI 5772R User Manual and Specifications

 | ni.com

Содержание NI 5772R

Страница 1: ...NI 5772...

Страница 2: ...and the NI 5772 This document also contains tutorial sections that demonstrate how to acquire data using a LabVIEW FPGA Example VI and how to create and run your own LabVIEW project with the NI 5772R...

Страница 3: ...se requirements and limits are designed to provide reasonable protection against harmful interference when the product is operated in the intended operational electromagnetic environment This product...

Страница 4: ...anels on page 33 Connecting Cables 1 Use any shielded 50 SMA cable to connect signals to the connectors on the front panel of your device 2 Use the SHH19 H19 AUX cable NI part number 152629 01 or 1526...

Страница 5: ...le from the Start menu and at ni com manuals Contains installation instructions for your NI FlexRIO system and specifications for your FPGA module NI 5772R User Manual and Specifications this document...

Страница 6: ...tion and data sheets for NI FlexRIO devices Front Panel and Connector Pinouts Table 2 shows the front panel connector and signal descriptions for the NI 5772 Caution To avoid permanent damage to the N...

Страница 7: ...AI 0 Analog input channel 0 50 single ended AI 1 Analog input channel 1 50 single ended TRIG Trigger input and output channel AUX I O Refer to Table 3 for the signal list and descriptions Caution Conn...

Страница 8: ...irectional SE DIO data channel 10 DIO Port 1 2 Bidirectional SE DIO data channel 11 GND Ground reference for signals 12 DIO Port 1 3 Bidirectional SE DIO data channel 13 PFI 0 Bidirectional SE DIO dat...

Страница 9: ...DC12D800RF DIO Port 1 WE Request DIO Port 1 Rd Data 0 3 DIO Port 1 Wr Data 0 3 DIO Port 1 WE Actual PFI 0 3 WE PFI 0 3 Rd Data PFI 0 3 Wr Data DIO Port 0 WE Request DIO Port 0 Rd Data 0 3 DIO Port 0 W...

Страница 10: ...l to the FPGA Adapter module socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external adapter module connector interface The following figure shows the relationship...

Страница 11: ...e grouped into two ports of four signals each and are accessed using a U8 data type and a Boolean write enable signal The four PFI signals are accessed individually using Boolean indicators Although r...

Страница 12: ...e Clock locked to an external Reference Clock through the REF IN connector Internal Sample Clock locked to an external Reference Clock though IoModSyncClock This CLIP also enables the user to synchron...

Страница 13: ...A embedded in the hardware At least one VI that runs on Windows and interacts with the LabVIEW FPGA VI Note In the LabVIEW FPGA Module software NI FlexRIO adapter modules are referred to as IO Modules...

Страница 14: ...select either Software or Data Edge If you select Software the VI acquires data every time you click the Software Trigger front panel button If you select Data Edge the VI acquires data every time an...

Страница 15: ...dule list The available CLIP for the NI 5772 is displayed in the General category of the Component Level IP pane If the information in the General category is dimmed select the Enable IO Module checkb...

Страница 16: ...pen FPGA VI Reference 5 In the Configure Open FPGA VI Reference dialog box select VI in the Open section 6 In the Select VI dialog box that opens select 5772SampleAcq FPGA vi under your device and cli...

Страница 17: ...function 18 Wire the error out output of the Read Write Control function to the error in input of the Close FPGA VI Reference function Your block diagram should now resemble the block diagram in the f...

Страница 18: ...IN front panel connector Note Do not connect an external Sample Clock with a frequency greater than 800 MHz to the CLK IN front panel connector to acquire data at rates greater than 800 MS s Instead u...

Страница 19: ...d Chassis fan speed is set to High In addition NI recommends using slot blockers and EMC filler panels in empty module slots to minimize temperature drift The NI 5772 uses NI LabVIEW and LabVIEW FPGA...

Страница 20: ...data4 ADC part number ADC12D800RF5 Absolute maximum voltage 10 VDC 21 dBm 7 1 Vpk pk Typical Specifications All specifications were tested in TIS Disabled mode unless otherwise specified DC offset AC...

Страница 21: ...tude at 10 MHz 3 dB 1 dB AC coupled 110 kHz 240 kHz DC coupled 0 kHz 0 kHz Table 9 Bandwidth And Spectral Performance Summary Mode Coupling Bandwidth 3 dB Bandwidth 1 dB SNR dB SFDR dBc THD dBc ENOB b...

Страница 22: ...upled N A N A N A N A N A N A Measured using a 1 dBFS signal at 187 MHz Related Information Analog Input Impedance on page 21 Analog Input Impedance Analog Input Impedance Figure 9 Analog Input Return...

Страница 23: ...G 2 G 2 4 G 0 9 10 M 1 8 Frequency Response Note Referenced at 10 MHz using 9 dBm Figure 11 AC Low Frequency Response Referenced to Amplitude at 10 MHz Frequency Hz Amplitude Response dB 6 0 7 0 3 0...

Страница 24: ...bled Non Muxed DC TIS Disabled Frequency Hz Amplitude Response dB Figure 13 DC Bandwidth Referenced to Amplitude at 10 MHz 100 0 200M 400M 600M 800M 1G 1 2G 1 4G 1 6G 95 90 85 80 75 70 65 60 55 50 45...

Страница 25: ...0 4 5 4 0 3 5 3 0 2 5 2 0 1 5 1 0 0 5 0 0 1 5 1 0 DC Ch0 TIS Disabled DC Ch1 TIS Disabled DC Ch0 TIS Enabled DC Ch1 TIS Enabled Spectral Measurements Figure 15 Noise Density Frequency Hz Noise Density...

Страница 26: ...20 M 400 M 0 20 30 40 10 0 70 60 50 90 80 110 100 10 Figure 17 Two Tone Spectral Measurement TIS Multiplexed Mode 182k Samples 10 Averages Frequency Hz Amplitude dBm 20 30 40 10 0 70 60 50 90 80 160 M...

Страница 27: ...IoModSyncClock Locked to Front Panel Free Running Uses a 10 MHz Wenzel OCXO P N 501 04609A as the reference signal Crosstalk Figure 19 AI Crosstalk Aggressor at 1 dBFS Victim Terminated to 50 7 Input...

Страница 28: ...DC Ch0 Aggressor Ch1 Victim DC Ch1 Aggressor Ch0 Victim Input Frequncy Hz Cross Talk dB Related Information Typical Specifications on page 19 Internal Sample Clock General Characteristics PLL part num...

Страница 29: ...dBm 7 1 Vpk pk Duty cycle 30 to 70 REF IN General Characteristics Number of channels 1 single ended Connector type SMA Frequency 10 MHz Input impedance 50 Input coupling AC Input voltage range 2 dBm 8...

Страница 30: ...ce logic Maximum VIL 0 8 V Maximum VIH 2 0 V Maximum VOL 0 4 V Minimum VOH 2 7 V Maximum VOH 3 6 V Zout 50 20 Iout DC 2 mA Pull down resistor 150 k Recommended operating voltage 0 3 V to 3 6 V Overvol...

Страница 31: ...ush Make sure that the hardware is completely dry and free from contaminants before returning it to service Environment Maximum altitude 2 000 m at 25 C ambient temperature Pollution Degree 2 Indoor u...

Страница 32: ...of the following electrical equipment safety standards for measurement control and laboratory use IEC 61010 1 EN 61010 1 UL 61010 1 CSA 61010 1 Note For UL and other safety certifications refer to the...

Страница 33: ...committed to designing and manufacturing products in an environmentally responsible manner NI recognizes that eliminating certain hazardous substances from our products is beneficial not only to the...

Страница 34: ...ct at ni com calibration National Instruments corporate headquarters is located at 11500 North Mopac Expressway Austin Texas 78759 3504 National Instruments also has offices located around the world F...

Страница 35: ...uments trademarks Other product and company names mentioned herein are trademarks or trade names of their respective companies For patents covering National Instruments products technology refer to th...

Отзывы: