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configuration, and how to access NI 5772 I/O nodes. For more detailed information about
acquiring data on your NI 5772R, refer to the streaming example available in NI Example
Finder.
Creating a Project
1. Launch LabVIEW, or if LabVIEW is already running, select
File
»
Create Project
.
2. In the
Create Project
dialog box, select
FPGA Template
and click
OK
. The new project
opens in the
Project Explorer
window.
3. Save the project as
5772SampleAcq.lvproj
.
Creating an FPGA Target VI
1. In the
Project Explorer
window, right-click
My Computer
and select
New
»
Targets
and Devices
.
2. In the
Add Targets and Devices on My Computer
dialog box, select the
Existing
Target or Device
option button and expand
FPGA Target
to display the target.
3. Select your device and click
OK
to load the target and target properties into the
Project
Explorer
window.
4. In the
Project Explorer
window, expand
FPGA Target (RIOx, PXI-79xxR)
.
5. Right-click
FPGA Target (RIOx, PXI-79xxR)
and select
New
»
FPGA Base Clock
.
6. In the
Resource
pull-down menu, select
IO Module Clock 0
and click
OK
.
7. Right-click
IO Module
in the
Project Explorer
window and select
Properties
.
8. Select theNI 5772 from the
IO Module
list. The available CLIP for the NI 5772 is
displayed in the
General
category of the
Component Level IP
pane. If the information
in the
General
category is dimmed, select the
Enable IO Module
checkbox.
9. Select in the
Name
list of the
Component Level IP
pane.
10. In the
Clock Selections
category, select
200 MHz Clock
from the pull-down menu for
Clk200
. Leave
Clk40
configured as the
Top-Level Clock
.
11. Click
OK
.
Note
Configuring these clocks is required for proper CLIP operation. Refer to
the NI 5772 CLIP topics in the
NI FlexRIO Help
for more information about
configuring your clocks.
12. In the
Project Explorer
window, right-click the FPGA target and select
New
»
VI
. A
blank VI opens.
13. Select
Windows
»
Show Block Diagram
to open the VI block diagram.
14. In the
Project Explorer
window, expand the
IO Module (NI 5771: NI 5771)
tree view.
15. Drag
AI 0 Data N–3
to the block diagram.
16. Click the handle on the bottom of the control node with the Positioning tool and drag the
edge down to expose the other signals,
AI 0 Data N–2...AI 0 Data N
control node.
17. Add a Timed Loop structure around the node.
18. Wire indicators to the output terminals of the
IO Module\AI 0 Data N–3...AI 0 Data N
.
19. Right-click the input node of the Timed Loop to wire an FPGA Clock Constant. Set this
constant to
Divided Sample Clock
.
14 |
NI 5772R User Manual and Specifications
| ni.com
Содержание NI 5772R
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