Technical Information
Chapter 3
GPIB-PRL User Manual
3-6
© National Instruments Corp.
P Mode Parallel Interface
Signal
Return
Signal
Direction
Description
Pin
Pin
1
19
STROBE*
IN
The STROBE* pulse tells the
GPIB-PRL that the data on the bus is
valid. The GPIB-PRL will read the
data in on the rising edge of
STROBE*. The STROBE* signal
should be asserted for at least 0.5
µ
sec.
2
20
DATA1
IN
These signals represent the data
3
21
DATA2
IN
byte being transferred. Each
4
22
DATA3
IN
signal is at a HIGH level when
5
23
DATA4
IN
data is a logical 1 and a LOW
6
24
DATA5
IN
level when data is a logical 0.
7
25
DATA6
IN
DATA1 is the lowest order bit
8
26
DATA7
IN
and DATA8 is the highest order
9
27
DATA8
IN
bit. This data should be stable on the
bus at least 0.5
µ
sec before
STROBE* is asserted and should
remain on the bus at least 0.5
µ
sec
after STROBE* is unasserted.
10
28
ACKNLG*
OUT
Indicates that the data has been
received by the GPIB-PRL and it is
ready to accept more data.
ACKNLG* will be asserted for a
minimum of 10
µ
sec.
11
29
BUSY
OUT
A HIGH signal indicates that the
GPIB-PRL is busy and cannot
accept more data. BUSY will be
high when a byte has been sent to the
GPIB-PRL but has not yet been
accepted.
19-30
-
GND
-
Twisted-pair ground return lines for
signals on pins 1-11.
