Chapter 3
Technical Information
© National Instruments Corp.
3-3
GPIB-PRL User Manual
The interface signal descriptions and timing relationships for the G mode
parallel port signals are shown in the following table.
G Mode Parallel Interface
Signal
Return
Signal
Direction
Description
Pin
Pin
1
19
STROBE*
OUT
The STROBE* pulse is used to
signal that data on the bus is valid.
Pulse width will be greater than 0.5
µ
sec.
2
20
DATA1
OUT
These signals represent the data
3
21
DATA2
OUT
byte being transferred. Each
4
21
DATA3
OUT
signal is at a HIGH level when
5
23
DATA4
OUT
data is a logical 1 and a LOW
6
24
DATA5
OUT
level when data is a logical 0.
7
25
DATA6
OUT
DATA1 is the lowest order
8
26
DATA7
OUT
bit and DATA8 is the highest
9
27
DATA8
OUT
order bit. The data will be stable on
the bus at least 0.5
µ
sec before
STROBE* is asserted and will
remain on the bus at least 0.5
µ
sec
after STROBE*is unasserted.
10
28
ACKNLG*
IN
Indicates that the data has been
received by the parallel device.
This signal should be active at least
0.5
µ
sec.
19-30
-
GND
-
Twisted-pair ground return lines for
signals on pins 1-10.
31
-
INIT*
OUT
Asserted when the GPIB-PRL
receives either a universal device
clear (DCL) or its listen address and
a selected device clear (SDC). This
signal will be asserted for
approximately 100
µ
sec.
33
-
GND
-
Same as for pins 19-30.
