Drivven, Inc.
Throttle Driver Module Kit
© Drivven, Inc. 2009
• Throttle Driver Module Kit User’s Manual • D000017 • Rev B
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Figure 5 shows the icon which represents throttle_rt_data_convert_revx.vi. This VI is used to
convert raw data from the FPGA to engineering units at the RT level. The outputs from this VI
should be wired to the throttle_rt_control.vi.
Figure 5. Throttle Data RT VI icon with leads.
Figure 6 shows the icon which represents throttle_rt_control.vi. This VI is used at the RT level
and accepts engineering unit data from the throttle_rt_data_convert_revx.vi along with additional
calibration values. One or two instances of this VI may be used, depending on the number of
throttle driver channels being utilized. The resulting period and pulsewidth output values should
be wired directly to the FPGA level to the throttle_revx.vi ThrottleControl cluster.
Figure 6. Throttle Control RT VI icon with leads.
The FPGA VI must be placed within a Single Cycle Loop (SCL) of a LabVIEW FPGA block
diagram. The SCL must execute at the default clock rate of 40 MHz.
The FPGA VI requires a pre-synthesized netlist file having a matching name and an extension of
.ngc. The netlist file must be located in the same directory as the matching VI. The installer will
place this file in the LabVIEW addons directory along with the FPGA VI.
