National Instruments AT-DIO-32F, Руководство пользователя

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Chapter 4 Programming
© National Instruments Corporation 4-51 AT-DIO-32F User Manual
The ports used for pattern generation should be configured for double-buffered outputs. Ports A
and B are double-buffered when the DBLBUFA and DBLBUFB bits in the CFG1 Register are
set. Ports C and D are double-buffered when the DBLBUFC and DBLBUFD bits in the CFG2
Register are set. Double-buffering means that the port has two buffers: a write buffer and an
output buffer. Writing to the port loads the write buffer. Contents of the write buffer are loaded
into the output buffer when the corresponding REQ is active. The output buffer is connected to
the digital I/O connector.
After a double-buffered port has been configured for handshaking, the first data pattern should be
written to the port. This write loads the data pattern into the write buffer of the port. When a
REQ is received, the data in the write buffer is transferred to the output buffer of the port, which
is connected to the digital I/O connector. The trailing edge of REQ also sets the DRDY bit for
the group. A polling routine, interrupt routine, or DMA can be used to detect the DRDY
condition and then write the data pattern to the port.
The double-buffered configuration sends the data pattern as soon as a REQ is received. In the
normal mode of operation, the data pattern is not dumped to the digital I/O connector until the
DRDY bit is detected and the data is written to the port.
The output of the counters is an active low pulse. The handshaking mode for pattern generation
must be set to active low REQ, trailing edge mode (INVREQ, PULSE, and EDGE are set).
Therefore, the latched data can be driven to the output lines during the active REQ pulse, and
new patterns can be written and latched after the active REQ duration.
Counter Output
(REQ*)
1 Clock
Pattern is dumped to I/O connector.
DRDY is set by this
trailing edge, and a new
pattern is written to
the buffer after DRDY
is set.
Figure 4-8. Pattern Generation
The programming steps to set up Counter 1 for pattern generation are as follows:
1. Set up Counter 1 for rate generation by writing hex 14 to the CNTRCMD Register for an 8-
bit count or by writing hex 34 to the CNTRCMD Register for a 16-bit count.
2. Write the count to the CNTR1 Register (see Table 4-5). If the count is a 16-bit value, write
the least significant byte first, then the most significant.
3. Write hex 10 to the CFG3 Register to enable Counter 1 for pattern generation (set the
CNT1HSEN bit).
4. Set up Group 1 to select double-buffered trailing pulse mode and to clear handshaking: write
hex 0378 to the CFG1 Register for an 8-bit Port A, or write hex 07F8 to the CFG1 Register
for a 16-bit Port A.