National Instruments AT-DIO-32F, Руководство пользователя

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Programming Chapter 4
AT-DIO-32F User Manual 4-48 © National Instruments Corporation
DMA Transfers
DMA increases transfer rates when handshaking data is transferred to or from the PC memory.
Each handshaking group can be assigned a separate DMA channel by setting the jumper on W1
(see Chapter 2, Configuration and Installation, for details).
There are two DMA modes: single-channel DMA for Groups 1 and 2 and double-channel DMA
using Group 1 handshaking. In single DMA mode, enable DMA transfers for each group by
setting DMAEN1 and DMAEN2 in the CFG1 and CFG2 Registers for Group 1 and Group 2,
respectively. The DMA request is asserted when the DRDY bit for the enabled group is set. The
DMA controller sends a terminal count when the value in its Terminal Count Register changes
from hex 0000 to hex FFFF. See the Interrupt Handling section earlier in this chapter for
information about generating an interrupt on the DMA terminal count. Refer to the IBM
Personal Computer AT Technical Reference manual for additional information about
programming the DMA controller.
In double DMA mode (DBLDMA bit set in the CFG3 Register), only Group 1 handshaking lines
are used for 16-bit DMA transfer, but both DMA channels should be enabled. DMA transfers
use the DMA channel for Group 1 until a DMA terminal count for Group 1 is received, then the
DMA transfers switch to the DMA channel for Group 2. When a DMA terminal count is
received for Group 2, the DMA transfers switch back to the Group 1 DMA channel. While one
DMA channel is acquiring data, the other channel can service the acquired data. The DMACH
bit in the STAT Register indicates which group's DMA channel is currently in use. If DMACH
is cleared, the DMA channel for Group 1 is currently in use; if DMACH is set, the DMA channel
for Group 2 is currently in use. If the DMA controller is programmed for auto-reinitialize mode,
the two DMA channels are continuously served in turn.
32-Bit Transfers
The four digital I/O ports are divided into two 16-bit groups: Group 1 and Group 2. Either 8-bit
or 16-bit operations can be performed on these groups. When the TRANS32 bit is set in the
CFG3 Register, 32-bit operations can also be performed. For 32-bit transfer mode, Groups 1 and
2 must be enabled for handshaking (DIOAEN, DIOBEN, DIOCEN, and DIODEN must be set).
The two groups should be programmed for identical configurations, with the same PULSE,
EDGE, LPULSE, and TS (TDELAY) values. Requests should not begin on the REQ1 line until
both groups are fully configured.
Configured in this way, the AT-DIO-32F can transfer data to or from all 32 of its data lines
simultaneously, using only the ACK1 and REQ1 handshaking lines. ACK2 and REQ2 can be
ignored. When a REQ1 is received, both DRDY1 and DRDY2 are set. When data has been
written or read for both Group 1 and Group 2, the ACK1 line asserts. Two write or read
operations are required for each 32-bit transfer: one to Group 1 for the lower word, and one to
Group 2 for the upper word of the 32-bit datum. Asserting both LRESET1 and LRESET2 resets
both groups and reinitializes the 32-bit transfer.
DMA can be used in conjunction with the 32-bit transfer mode for high-speed 32-bit transfers.
The Group 1 data transfer and the Group 2 data transfer both use the DMA channel selected for
Group 1. The count written to the DMA Terminal Count Register of the DMA controller should
be twice the selected number of 32-bit transfers to be performed. If double DMA mode is used,
the DMA channel used for the transfers swaps after each terminal count.