National Instruments AT-DIO-32F, Руководство пользователя

Страница: 99 / 155

Programming Chapter 4
AT-DIO-32F User Manual 4-52 © National Instruments Corporation
5. Write hex 0278 (for 8-bit) or 0678 (for 16-bit) to the CFG1 Register to finish clearing
handshaking.
6. Write hex A410 to the CFG3 Register to enable Counter 1 for pattern generation and to set
Group 1 in write mode (set the WRITEA and WRITEB bits).
7. Write hex A414 to the CFG3 Register to start pattern generation on Counter 1 (set the
CNT1EN bit).
The counter is loaded with the initial count in the CNTR1 Register, and when the CNT1EN bit is
set, the counter is decremented by 1 on each clock pulse. REQ1 is initially high. When the
counter decrements to 1, REQ1 goes low for one clock pulse and then returns to high. The
counter is then reloaded from the CNTR1 Register and decrementing continues. The trailing
edge of REQ1 causes the DRDY1 bit to go high. The DRDY1 bit can be monitored by a polling
loop, by interrupt request generation, or by DMA request generation. With one of these
methods, data can then be written out to Port A.
The programming steps to set up Counter 2 for pattern generation are as follows:
1. Set up Counter 2 for rate generation by writing hex 54 to the CNTRCMD Register for an 8-
bit count or by writing hex 74 to the CNTRCMD Register for a 16-bit count.
2. Write the count to the CNTR2 Register (see Table 4-5). If the count is a 16-bit value, write
the least significant byte first, then the most significant.
3. Write hex 20 to the CFG3 Register to enable Counter 2 for pattern generation (set the
CNT2HSEN bit).
4. Set up Group 2 for trailing pulse mode and to clear handshaking: write hex 0378 to the
CFG2 Register for an 8-bit Port C, or write hex 0778 to the CFG2 Register for a 16-bit Port
C.
5. Write hex 0278 (for 8-bit) or 0678 (for 16-bit) to the CFG2 Register to finish clearing
handshaking.
6. Write hex 4820 to the CFG3 Register to enable Counter 2 for pattern generation and to set
Group 2 in write mode (set the WRITEC and WRITED bits).
7. Write hex 003 to the CFG4 Register to set double buffer output of Port D.
8 Write hex 4828 to the CFG3 Register to start pattern generation on Counter 2 (set the
CNT2EN bit).
The counter is loaded with the initial count in the CNTR2 Register, and when the CNT2EN bit is
set, the counter is decremented by 1 on each clock pulse. REQ2 is initially high. When the
counter decrements to 1, REQ2 goes low for one clock pulse and then returns to high. The
counter is then reloaded from the CNTR2 Register and decrementing continues. The trailing
edge of REQ2 causes the DRDY2 bit to go high. The DRDY2 bit can be monitored by a polling
loop, by interrupt request generation, or by DMA request generation. With one of these
methods, data can then be written out to Port C. To use DMA for pattern generation, you must
set the DMAEN bit, then program the DMA controller between steps 5 and 6.