NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH
47
11.3.21 PLL
Output
Signals Register
The PLL Output Signals Register shows the state of the PLL Output signals.
Table 43:
PLL_Outp Register
PLL Output Signals - Address 0x14
Default value 0x00
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Func -
-
-
HOLD-
OVER
LOCK
REF_FAIL
2
REF_FAIL
1
REF_FAIL
0
Table 44:
PLL_Outp - Register Bits
Bit
Name
Function
0
REF_FAIL0
A logic high shows that the Reference, that is connected
to REF0 of the PLL has failed
1
REF_FAIL1
A logic high shows that the Reference, that is connected
to REF1 of the PLL has failed
2
REF_FAIL2 A logic high Shows that the external Reference, that is
connected to REF2 of the PLL has failed
3
LOCK
This output goes to a logic high when the PLL is
frequency locked to the selected input reference
4
HOLDOVER This bit goes to a logic high whenever the PLL goes into
holdover mode
[7..5] -
no
function
write as 0 and ignore when read
