Multitech MultiVOIP MVPGK1 Gatekeepers, Руководство пользователя по оборудованию

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MultiVOIP Gatekeeper User Guide
Esc: Quit
F1: Help
F5: Old Values
F6: Load BIOS Defaults
F7: Load Setup Defaults
Pu/Pd/+/-: Modify
(Shift) F2: Color
:SELECT ITEM
ROM / PCI / ISA BIOS (2A59FP6C)
BIOS FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration :Enable
DRAM Timing : 70 ns
DRAM RAS# Precharge Time :4
DRAM R/W Leadoff Timing :7/6
Fast RAS# to CAS# Delay :3
DRAM Read BUrst (EDO/FPM) :x333/x444
DRAM Write Burst Timing :x333
Turbo Read Leadoff :Disabled
DRAM Speculative Leadoff :Disabled
Turn-Around Insertion :Disabled
ISA Clock :PCICLK/4
System BIOS Cacheable :Disabled
Video BIOS Cacheable :Disabled
8-Bit I/O Recovery Time :1
16-Bit I/O Recovery Time :1
Memory Hole at 15M-16M :Disabled
Peer Concurrency :Enabled
Chipset Special Features :Enabled
DRAM ECC/Parity Select :Parity
Memory Parity / ECC Check :Auto
Single Bit Error Report :Enabled
L2 Cache Cacheable Size :64MB
Chipset NA# Asserted :Enabled
Pipeline Cache Timing :Faster
Passive Release :Enabled
Delayed Transaction :Disabled
Figure C-7. Chipset Features Setup
By moving cursor to the desired field and pressing < F1 > key, all values for that field will be displayed.
Auto Configuration Function:
When this option is Enabled, the BIOS automatically configures cache and clock settings based on
detection of the CPU clock speed. The user cannot change the other parameters. Set this option to
Disabled to do manual setting of DRAM , cache, and I/O bus clock operating parameters. Enabled
is the default.
DRAM Settings
The first chipset settings deal with CPU access to dynamic random access memory (DRAM). The default
timings have been carefully chosen and should only be altered if data is being lost. One data-loss
scenario that relates to DRAM timing values occurs when the computer contains mixed-speed DRAM
chips; greater delays may be required to preserve the integrity of the data held in the slower memory
chips and, consequently, data may be lost.
ISA Clock:
Defines the clock value for the ISA bus. Usually, the ISA bus clock should be programmed to 8 Mhz. For
example, when the PCI clock is 33MHz, choose PCICLK/4. PCICLK/4 is the default value.
Cache Features
System BIOS Cacheable
When enabled, accesses to the system BIOS ROM addressed at F0000H-FFFFFH are cached.
Enabled BIOS access cached
Disabled BIOS access not cached
Disabled is the default.
Video BIOS Cacheable
As with caching the System BIOS above, enabling the Video BIOS cache will cause access to video BIOS addressed
at C0000H to C7FFFH to be cached.
Enabled Video BIOS access cached
Disabled
Video BIOS access not cached
Disabled is the default.
PCI and IDE Configuration
8 Bit I/O Recovery Time