Motorola MC68341 Скачать руководство пользователя | Manualshive

Страница: 19 / 20

background image

MOTOROLA

MC68341 USER’S MANUAL ADDENDUM

19

Case 864A-03

ÇÇÇÇÇ

ÇÇÇÇÇ

ÇÇÇÇÇ

ÇÇÇÇÇ

ÇÇÇÇÇ

ÉÉÉ

ÉÉÉ

ÉÉÉ

ÉÉÉ

ÉÉÉ

DETAIL C

–H–

–B–

–A–

–D–

L

Y

DETAIL A

B

V

L

Z

A

S

!

!

!

!

!

!

!

!

DETAIL A

G

P

–A–, –B–, –D–

B

B

–H–

–C–

E

C

M

U

W

K

X

Q

R

T

H

!

!

D

N

F

J

BASE
METAL

SECTION B–B

DETAIL C

"!

! " !

'

" ! "

"# ! " " ""

! " %" " %

" &"! " !" ' " "

"" " "

"#! " " "

"#

!! ! $ " " "

!"

!! " #

" #! % " #! !

! !!

# !" "

" "#

! ! " #

" #! % " #!

! "" &!! "

! " &# " "

" " " %

#! " "

!

!

!

TOP &

BOTTOM

«
...
17
18
19
20
»

Содержание MC68341

Страница 1: ...t paragraph change the first two lines to The CPU32 restricts all operands both data and instructions to be word aligned That is word and long word operands must be located on a word boundary Long word operands do not have to be long word aligned 3 WE on Fast Termination On page 3 17 Figure 3 6 UWE and LWE do not assert for fast termination writes 4 Write Cycle Timing Waveforms On page 3 25 the M6...

Страница 2: ... ADDENDUM 2 Figure 3 12 M68300 Write Cycle timing WORD WRITE S0 S2 S4 S0 S2 S4 CLKOUT A31 A2 A1 A0 FC3 FC0 SIZ1 SIZ0 R W AS UDS LDS DSACK DTC BYTE WRITE D15 D8 D7 D0 S0 S2 S4 OP3 OP3 WORD BYTE BYTE WRITE CSx DS AS68K OP2 OP3 UWE LWE ...

Страница 3: ...L ADDENDUM 3 Figure 3 14 M68000 Write Cycle Timing WORD WRITE S0 S2 S4 S0 S2 S4 CLKOUT A31 A2 A1 A0 FC3 FC0 SIZ1 SIZ0 R W AS UDS DSACK DTC BYTE WRITE D15 D8 D7 D0 S0 S2 OP3 OP3 WORD BYTE BYTE WRITE CSx DS AS68K OP2 OP3 UWE LDS LWE ...

Страница 4: ...ly This is also true for level sensitive external interrupts which are autovectored us ing either the AVEC signal or the AVEC register since the SIM will not respond to an interrupt arbitration cycle on the IMB if the external interrupt at that level has been removed External interrupts configured as edge sen sitive only have to be held a minimum of 1 5 clocks see section 4 3 5 8 PROGRAMMABLE INTE...

Страница 5: ...e specified in the DMA configuration for the source and destination arbitration can occur between each of the multiple operand accesses which must be made to the smaller port for each operand access to the larger port The RMC read write sequences for a TAS instruction is also indivisible to guarantee data coherency Arbitration is allowed between each op erand transfer of a multi operand operation ...

Страница 6: ...function is needed ground EXTAL if the RTC is not used Also the clock input on EXT CLK should be very clean when the 32KHz oscillator is used Excessive undershoot or overshoot as well as fast edge rates may result in coupling to the adjacent XTAL input affecting operation of the 32kHz oscillator 22 Recommended XFC Capacitor Values On page 4 12 third paragraph and page 11 2 last paragraph The XFC c...

Страница 7: ...7263 13 229 459 1835 3670 7340 918 1835 7340 14680 29360 14 246 492 1966 3932 7864 983 1966 7864 15729 31457 15 262 524 2097 4194 8389 1049 2097 8389 16777 33554 16 279 557 2228 4456 8913 1114 2228 8913 17826 35652 17 295 590 2359 4719 9437 1180 2359 9437 18874 37749 18 311 623 2490 4981 9961 1245 2490 9961 19923 39846 19 328 655 2621 5243 10486 1311 2621 10486 20972 41943 20 344 688 2753 5505 110...

Страница 8: ...3 721 1442 5767 11534 23069 2884 5767 23069 46137 92275 44 737 1475 5898 11796 23593 2949 5898 23593 47186 94372 45 754 1507 6029 12059 24117 3015 6029 24117 48234 96469 46 770 1540 6160 12321 24642 3080 6160 24642 49283 98566 47 786 1573 6291 12583 25166 3146 6291 25166 50332 100663 48 803 1606 6423 12845 25690 3211 6423 25690 51380 102760 49 819 1638 6554 13107 26214 3277 6554 26214 52429 104858...

Страница 9: ...lizes the MBAR register with AS7 set This prevents the ad dress decode for the internal 4K register block from responding to CPU space accesses In particular it pre vents the register block decode of FFFFFxxx from interfering with IACK cycles address FFFFFFFx and possibly corrupting the vector number returned Normal interrupt acknowledge operation for the internal mod ules is not affected by this ...

Страница 10: ... Range The valid range for the MONTH register on page 4 43 is 1 12 with 1 corresponding to January and 12 cor responding to December 33 SIM41 Example Code On page 4 49 about mid page change MOVEQ 8 1 D0 to MOVEQ 16 1 D0 to initialize all 8 chip se lects 34 Bus Error Stack Frame On page 5 61 in the next to last paragraph delete the internal transfer count register is located at SP 10 and the SSW is...

Страница 11: ...lete operand transfer completes even if operand and memory sizing results in multiple bus cycles For a DREQx assertion during an idle bus period bus state S0 of the DMA bus cycle starts 2 5 clocks after the clock falling edge which DREQx is recognized on The maximum latency from the clock falling edge that DREQx is recognized on to the falling edge that AS for the DMA cycle asserts from is shown i...

Страница 12: ... it being held for only 1 clock edge Note 1 of Figure 6 14 should be deleted 47 Typo in DAPI On page 6 26 for DAPI 1 the DAR is incremented according to the destination size not the source size 48 Additional note on DMA limited rate operation On page 6 27 in the BB Bus Bandwidth Field The DMA active count increments only when the DMA channel is the bus master each channel has its own counter If a ...

Страница 13: ...tails Add to the RTSA and RTSB descriptions on page 7 6 The RTSx outputs are active low signals they drive a logic 0 when set and a logic 1 when cleared RTSx can be set output logic level 0 by any of the following Writing a 1 to the corresponding bit in the OPSET register 71E Issuing an Assert RTS command using command register CR If RxRTS 1 set by receiver FIFO transition from FULL to not FULL RT...

Страница 14: ...acter completes transmission i e TxEMP The serial module logic latches this bit and ap pends it to the data character when the character is transferred from the transmit buffer to the serial output shift register Once this transfer occurs as indicated by the TxRDY assertion the A D bit in MR1 can be changed without affecting the character in progress The proper programming sequence to change the A...

Страница 15: ...inning of this document for information on accessing AESOP 62 Additional Note on Oscillator Layout Guidelines Add to the Processor Clock Circuitry page 11 1 and Serial Interface page 11 4 sections In general use short connections and place external oscillator components close to the processor Do not route other signals through or near the oscillator circuit especially high frequency signals like C...

Страница 16: ...Duty Cycle in External Clock w PLL mode On page 12 7 External Clock With PLL Mode The input clock 20 80 duty cycle for external clock with PLL mode can be used when the VCO is not turned off during LPSTOP During LPSTOP with the VCO turned off the input clock is used for clocking the SIM and must meet the tighter duty cycle requirements outlined for External Clock Mode Without PLL 69 Clock Skew Not...

Страница 17: ... in Section 11 with the following ordering information 74 Upper and Lower Data Strobes In paragraph 3 2 8 page 3 6 change D15 D0 to D15 D8 and D8 D0 to D7 D0 75 Figure 3 2 Change Note 1 to reference MC68341 instead of MC68340 76 Figure 4 8 The Periodic Interrupt Control Register PICR and Periodic Interrupt Timing Register PITR should be 1 word instead of 2 bytes Disregard the Scale Select Register...

Страница 18: ...e should be 6 4 not 6 5 80 Page 9 19 The timing diagrams reference as Figures 9 24 9 27 should be changes to 12 22 12 25 81 Page 9 29 DT Delay A value of 1 enable this bit and 0 disables it 82 Package Dimensions The package dimension drawing on page 13 3 should be discarded and replaced with the following drawing ...

Страница 19: ... MANUAL ADDENDUM 19 Case 864A 03 ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ DETAIL C H B A D L Y DETAIL A B V L Z A S DETAIL A G P A B D B B H C E C M U W K X Q R T H D N F J BASE METAL SECTION B B DETAIL C TOP BOTTOM ...

Страница 20: ...lidated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure o...

Отзывы:

Нет отзывов

Похожие инструкции для MC68341

Бренд: Omnia Страницы: 102

Бренд: Sangoma Страницы: 6

Бренд: QSC Страницы: 28

Бренд: mikroElektronika Страницы: 3

Бренд: SMART Страницы: 15

Бренд: Alesis Страницы: 46

Urban Wireless CC-VT240W

Бренд: Cateye Страницы: 15

Бренд: hilscher Страницы: 154

iCE40 SPRAM Series

Бренд: Lattice Semiconductor Страницы: 12

Kontron SMARC-sXEL

Бренд: S&T Страницы: 108

Бренд: Doremi Страницы: 15

Бренд: OPTO 22 Страницы: 28

Power System S914

Бренд: IBM Страницы: 48

Бренд: Baikal Miner Страницы: 14

Data Capture Board CLC-CAPT-PCASM

Бренд: National Semiconductor Страницы: 15

Бренд: Cypress Semiconductor Страницы: 28

Бренд: HighPoint Страницы: 12

Бренд: Cutting Edge Страницы: 92

Бренды по названию

0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Популярные бренды

Загрузить еще бренды