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OVERVIEW
CHAPTER1 OVERVIEW
This User's Manual describes the specifications, handling, and programming methods for
the type QD63P6 multichannel high-speed counter module used together with the
MELSEC-Q series CPU module.
The QD63P6 can use the following methods in 1-phase/2-phase pulse inputs.
For details of the input methods, refer to Section 5.1.
Figure 1.1 shows the general operation of the QD63P6.
Figure 1.1 General operation of the QD63P6
•1 multiple of 1 phase pulse
input
•2 multiples of 1 phase pulse
input
•CW/CCW
•1 multiple of 2 phases pulse
input
•2 multiples of 2 phases pulse
input
•4 multiples of 2 phases pulse
input
QD63P6
Programmable
controller CPU
QCPU (Q mode)
CH1
1)
Pulse
CH2
1)
Pulse
CH3
1)
Pulse
CH4
1)
Pulse
CH5
1)
Pulse
CH6
1)
Pulse
3)
3)
3)
3)
3)
3)
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
1) Pulses input to the QD63P6 are counted.
2) The status of the I/O signals and buffer memory of the QD63P6 can be checked with the
sequence program.
Also, start, stop, preset, and coincidence detection of the count can be executed.
3) An interrupt request can be executed to the programmable controller CPU at counter
value coincidence detection.
2) Reading/writing
the I/O signals and
buffer memory
