Mitsubishi Electric DLP XD8100U, Руководство по обслуживанию

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- B1 -
IC BLOCK DIAGRAMS
IC2K0 PQ1M255M2SPQ IC2L0 TAR5S15
IC520, IC521 NC7SZ157P6X(PBF)
Function Table
H : HIGH Logic Level
L : LOW Logic Level
Inputs Output
S I1 X=(I0)•(S)+(I1)•(S)
L
L H
L
H L
X
X
L
I0
H
L
X
H H X X
2
0
1
5
1
3
6
4
I1
GND
I0
S
VCC
Z
C
L
A
M
P
&
B
I
A
S
S
W
S
W
S
W
S
W
S
W
AGC
AMP1
Y-IN1
(CVBS)
Y-IN2
(S-Y)
Y-IN3
(D1/D2-Y)
C-IN
(S-C)
G-IN
CVBS/Y
C
C/G
Cb/B
Cr/R
Cb-IN
B-IN
Cr-IN
R-IN
8bit
ADC
TOF/ACC
Color System Det.
Multi Color Decorder
YCS
RGB–>CbCr
Matrix
LPF
VBI Data Det.
ID1,WSS,CCD,S/N,Macrovision
CbCr SW
Color Level
Contrast/Brightness
NR Mode:
3DNR
Memory
Clock
Gene.
42M
X'tal
Reference
Clock
IIC-BUS
SCL SDA
CTI/TINT
Color Level
LTI/Contrast
Brightness
Sharpness
Mix
FB SW
ITU-R656
/601
Encode
656/601
Format
Vertical
Enhance
AGC Det
AGC AMP2
8bit
ADC
NTSC 3D Comb
Motion Det.
3 Line Comb
8bit
ADC
8bit
ADC
FB-IN Input I/F
Sync Sep
H/V Timing
HD VD
Digital I/F
CbCr
(D1)
Y(D2)
Y
(D1)
Y
(D1)
CbCr
Y
CbCr
Y
CbCr
Y
CbCr
Y
CbCr
CbCr(D1)
CbCr(D2)
CbCr
IC522 RD74LVC14BTELL
6A
6Y
5A
5Y
4A
4Y
VCC 1A
1Y
2A
2Y
3A
3Y
GND
INPUT
A
OUTPUT
Y
H
L
L
H
FUNCTION TABLE
1
2
3
4
5
13
12
11
14
10
9
8
6
7
ANALOG PCB-MAIN (1/9)
IC2A0 TC90103AFG
IC530 MAXT
NC 1
2
3
4
8
7
6
5
IN
NO
COM
V+
V–
GND
EN
EN IN NC NO
0 0 ON OFF
0 1 OFF ON
1 X OFF OFF
X = Don't Care
Function Table
IC540 24LCS21AT-I*SNG
WP
HV
Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Laches
YDEC
Sence Amp.
R/W Control
SCL
VCC
VSS
SDA
8
4
3
5 6
VCLK
7
CONTROL
Vo
Nr
GND
Vin
Vc
4 5
1
3
2
5
4
1
2
3
VIN
VOUT NOISE
GND
Control Level
Function Table
OFF
ON HIGH
LOW
Operation
CONTROL