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- B3 -
IC6A0 MST3361CMK-LF-170
IC6M0 24LC02BT-I*SNG
IC6L0 RT9701-GB
HDCP Cipher
HDCP Keys
XOR Mask
Test Pattern
Generatior
CSC
HDMI
RX
Clamp
PLL
Sync
Processing
Host Interface
and
Power Management
ADC
30
30
30
MUX
Sync
Stripper
M
U
X
Clock
Generator
30
30
Output
Formatting
Audio
Stream
FIELD/GPO
VSOUT
SPDIFO
Serial Audio Bus
HSOUT
SOGOUT/DE
DATACK
DATA[29:0]
DDCB SCL
Analog Input
HDMI LINK A
HDMI LINK B
Analog SOGIN0
Analog HSYNC0
Analog VSYNC0
DDCB SDA
DDCA SCL
DDCA SDA
SCL SDA
A0
XIN
XOUT
M
U
X
M
U
X
ADC
DSP
Control
Thermal
Detection
Current
Limit
Bias
Charge
Pump
Oscillator
NMOSFET
RS
3
1,5
2
EN
VIN
VOUT
GND
4
WP
HV
Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Laches
YDEC
Sence Amp.
R/W Control
I/O
SCL
VCC
VSS
SDA
8
4
7
5
6
IC6S0 MAX
/-
/-
/-
/-
/-
/-
/-
/-
TERMINATED
3.3V CML
TERMINATED
3.3V CML
TERMINATED
3.3V CML
TERMINATED
3.3V CML
EQCONTROL
OUTON
OUTLEVEL
CLKOS
DRIVER
DRIVER
DRIVER
DRIVER
LIMITING
AMPLIFIER
LIMITING
AMPLIFIER
LIMITING
AMPLIFIER
LIMITING
AMPLIFIER
ADAPTIVE
EQ
ADAPTIVE
EQ
ADAPTIVE
EQ
INPUT
BUFFER
INPUT
BUFFER
INPUT
BUFFER
INPUT
BUFFER
CLOCK LOS
DETECTOR
11,10
26,27
30,31
34,35
22,21
17
40
39
14,15
18
3,2
7,6
Содержание DLP XD8100U
Страница 9: ... 4 PCB LOCATION Fig 1 1 2 7 5 8 3 4 6 9 10 11 12 13 14 ...
Страница 11: ... 6 EXPOSED VIEW Fig 2 1 5 3 Fx1 Hx2 7 2 Dx2 Cx3 8 Ex1 Gx1 1 Ax1 4 6 Kx2 Jx1 Bx1 9 DLP ASSY ...
Страница 13: ... 8 Chassis ASSY 1 Fig 2 2 1 Ax10 Bx2 Cx2 4 5 Fx5 Gx2 Hx2 6 8 9 2 Kx5 Lx3 3 Dx2 7 Jx1 Ex2 ...
Страница 15: ... 10 1 Ax5 4 5 6 8 7 Bx2 Cx4 Dx2 Ex4 Hx2 11 2 3 10 9 Hx2 Fx1 Gx2 Chassis ASSY 2 Fig 2 3 ...
Страница 22: ... 17 1 2 3 4 5 6 7 8 9 10 E x 2 C x 2 D x 2 B x 2 A x 2 Filter ASSY Fig 2 7 ...
Страница 146: ... MEMO ...