MiTAC Mio336i, Руководство по обслуживанию

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Mio336i PDA Maintenance
Mio336i PDA Maintenance
4.1 Intel PXA255 (Cotulla) Application Processor
Signal Name Type Description
Crystal and Clock Pins
PXTAL
OA 3.6864 MHz crystal input. No external caps are required.
PEXTAL
IA 3.6864 MHz crystal output. No external caps are required.
TXTAL OA 32 KHz crystal input. No external caps are required.
TEXTAL IA 32 KHz crystal output. No external caps are required.
L_DD[12]/GPIO[7
0] ICOCZ LCD display data. (output) Transfers pixel information from the LCD
controller to the external LCD panel.
RTC clock. (output) Real time clock 1 Hz tick.
L_DD[13]/GPIO[7
1[ ICOCZ
LCD display data.
(output) Transfers pixel information from the LCD
controller to the external LCD panel.
3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator.
L_DD[14]/GPIO[7
2] ICOCZ LCD display data. (output) Transfers pixel information from the LCD
controller to the external LCD panel.
32 KHz clock. (output) Output from the 32 KHz oscillator.
48MHz/GP[7] ICOCZ
48 MHz clock.
(output) Peripheral clock output derived from the PLL.
Note: This clock is only generated when the USB unit clock enable is
set.
RTCCLK/GP[10] ICOCZ Real time clock. (output) 1 Hz output derived from the 32 KHz or
3.6864 MHz output.
3.6MHz/GP[11] ICOCZ 3.6864 MHz clock. (output) Output from 3.6764 MHz oscillator.
32KHz/GP[12] ICOCZ 32 KHz clock. (output) Output from the 32 KHz oscillator.
Miscellaneous Pins
BOOT_SEL
[2:0]
IC
Boot select pins.
(input) Indicate the type of boot device.
nBATT_FAULT IC Main Battery Fault. (input) Signals that main battery is low or
removed. Assertion causes PEX255 Porcessor to enter sleep mode or
force an imprecise data exception, which cannot be masked. PXA255
processor will not recognize a wake-up event while this signal is
asserted. Minimum assertion time for nBATT_FAULT is 1ms.
nVDD_FAULT IC VDD Fault. (input) Signals that the main power source is going out of
regulaion. NVDD_FAULT causes the PXA255 processor to enter sleep
mode or force an imprecise data exception, which cannot be masked.
NVDD_FAULT is ignored after a wake-up event until the power supply
timer completes (approximately 10ms). Minimum assertion time for
nVDD_FAULT is 1ms.
nRESET
IC Hard reset. (input) Level-sensitive input which used to starts the
processor from a known address. Assertion terminates the current
instruction abnormally and causes a reset. When nRESET is driven high,
the processor starts execution from address 0. nRESET must remain low
until the power supply is stable and the internal 3.6864 MHz oscillator
has stabilized.
Signal Name Type Description
PWR_EN OC P ower enable for the power supply. (output) When negated, it signals
the power supply to remove power to the core because the system is
entering sleep mode.
nRESET_OUT OC Reset Out. (output) Asserted when nRESET is asserted and de-asserts
after nRESET is de-asserted but before the first instruction fetch.
NRESET_OUT is also asserted for “soft” reset events: sleep, watchdog
reset, or GPIO reset.
JTAG and Test Pins
nTRST
IC JTAG test interface reset. Resets the JTAG/debug port. If JTAG/debug
is used, drive nTRST from low to high either before or at the same time
as nRESET. If JTAG is not used, nTRST must be either tied to nRESET
or tied low.
TDI IC JTAG test data input. (input) Data from the JTAG controller is sent to
the PXA255 processor using this pin. This pin has an internal pull-up
resistor.
TDO
OCZ JTAG test data output. (output) Data from the PXA255 processor is
returned to the JTAG controller using this pin.
TMS IC JTAG test mode select. (input) Selects the test mode required from the
JTAG controller. This pin has an internal pull-up resistor.
TCK IC JTAG test clock. (input) Clock for all transfers on the JTAG test
interface.
TEST
IC Test mode. (input) Reserved. Must be grounded.
TESTCLK IC
Test clock.
(input) Reserved. Must be grounded.
Power and Ground Pins
VCC
SUP Positive supply for internal Logic. Must be connected to the low
voltage supply on the PCD.
VSS SUP Ground supply for internal logic. Must be connected to the common
ground plane on the PCB.
PLL_VCC SUP Positive supply for the PLLs and Oscillators. I Must be connected to
the common low voltage supply.
PLL_VSS SUP Ground signal for PLLs. Must be connected to the common ground
plane on the PCB.
VCCQ
SUP
Positive supply for all CMOS I/O, except memory bus and PCMCIA
pins.
Must be connected to the common 3.3v supply on the PCB.
VSSQ SUP Ground supply for all CMOS I/O except memory bus and PCMCIA
pins.
Must be connected to the common ground plane on the PCB.
VCCN SUP Positive supply for memory bus and PCMCIA pins. Must be
connected to the common 3.3v or 2.5v supply on the PCB.
VSSN
SUP Ground supply for memory bus and PCMCIA pins. Must be
connected to the common ground plane on the PCB.