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Mio336i PDA Maintenance
Mio336i PDA Maintenance
Low power consumption :
- Less then 1.6mA at 5V/4MHz
- Typically 15
µ
A at 3V/32KHz
- Typically 1
µ
A during sleep mode
1K × 13 bits on chip ROM
One security register to prevent intrusion of OTP memory codes
One configuration register to accommodate user’s requirements
48× 8 bits on chip registers (SRAM, general purpose register)
2 bi-directional I/O ports
5 level stacks for subroutine nesting
8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt
Two clocks per instruction cycle
Power down (SLEEP) mode
Three available interruptions
- TCC overflow interrupt
- Input-port status changed interrupt (wake up from sleep mode)
- External interrupt
Programmable free running watchdog timer
8 programmable pull-high pins
7 programmable pull-down pins
Содержание Mio336i
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