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Mio336i PDA Maintenance
Mio336i PDA Maintenance
1.3.2.2 RAM : Synchronous DRAM (SDRAM)
SAMSUNG 256M-bit (16Mx16) Synchronous DARM
The K4S561633C is 268, 435, 456 bits synchronous high data rate Dynamic RAM organized as 4 x 4, 196, 304
words by 16bits, fabricated with SAMSUNG high performance CMOS technology. Synchronous design allows
precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the same device to be useful
for a variety of high bandwidth, high performance memory system applications.
Description
3.0V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS latency (1& 2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
EMRS cycle with address key programs
All inputs are sampled at the positive going edge of the system clock
DQM for masking
Feature :
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