MiTAC Mio336i, Руководство по обслуживанию

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Mio336i PDA Maintenance
Mio336i PDA Maintenance
4.1 Intel PXA255 (Cotulla) Application Processor
4. Pin Descriptions of Major Components
Signal Name Type Description
Memory Controller Pins
MA[25:0]
OCZ Memory address bus. (output) Signals the address requested for
memory accesses.
MD[15:0] ICOCZ Memory data bus. (output) Lower 16-bit of the data bus.
MD[31:16] ICOCZ Memory data bus. (input/output) Used for 32-bit memories.
nOE OCZ Memory output enable. (output) Connect to the output enables of
memory devices to control data bus driver.
nWE OCZ Memory write enable. (output) Connect to the write enables of memory
devices.
nSDCS[3:0] OCZ
SDRAM CS for banks 3 through 0.
(output) Connect to the chip select
(CS) pins for SDRAM. For the PXA255 processor nSDCS0 can be Hi-Z,
nSDCS1-3 cannot.
DQM[3:0] OCZ SDRAM DQM for data bytes 3 through 0. (output) Connect to the
data output mask enables (DQM) for SDRAM.
nSDRAS OCZ SDRAM RAS. (output) Connect to the row address strobe (RAS) pins
for all banks of SDRAM.
nSDCAS OCZ SDRAM CAS. (output) Connect to the column address strobe (CAS)
pins for all banks of SDRAM.
SDCKE[0] OC Synchronous Static Memory clock enable. (output) Connect to the
CKE pins of SMROM. The memory controller provides control register
bits for de-assertion.
SDCKE[1] OC SDRAM and/or Synchronous Static Memory clock enable. (output)
Connect to the clock enable pins of SDRAM. It is de-asserted during
sleep. SDCKE[1] is always de-asserted upon reset. The memory
controller provides control register bits for de-assertion.
SDCLK[0] OC Synchronous Static Memory clock. (output) Connect to the clock
(CLK) pins of SMROM. It is driven by either the internal memory
controller clock, or the internal memory controller clock divided by 2. At
reset, all clock pins are free running at the divide-by-2 clock speed and
may be turned off via free-running control register bits in the memory
controller. The memory controller also provides control register bits for
clock division and de-assertion of each SDCLK pin. SDCLK[0] control
register assertion bit defaults to on if the boot-time static memory bank 0
is configured for SMROM.
nCS[0] ICOCZ Static chip select 0. (output) Chip select for the boot memory. NCS[0] is
a dedicated pin.
RRD/nWR OCZ Read/Write for static interface. (output) Signals that the current
transaction is a read or write.
Signal Name Type Description
SDCLK[1] OCZ
SDCLK[2]
OC
SDRAM Clocks (output) Connect SDCLK[1] and SDCLK[2] to the
clock pins of SDRAM in bank pairs 0/1 and 2/3, respectively. They are
driven by either the internal memory controller clock, or the internal
memory controller clock divided by 2. At reset, all clock pins are free
running at the divide-by-2 clock speed and may be turned off via
free-running control register bits in the memory controller. The memory
controller also provides control register bits for clock division and
de-assertion of each SDCLK pin. SDCLK[2:1] control register assertion
bits are always de-asserted upon reset.
nCS[5]/GPIO[33] ICOCZ
nCS[4]/GPIO[80] ICOCZ
nCS[3]/GPIO[79] ICOCZ
nCS[2]/GPIO[78] ICOCZ
nCS[1]/GPIO[15] ICOCZ
Static chip selects. (output) Chip selects to static memory devices such
as ROM and Flash. Individually programmable in the memory
configuration registers.
nCS[5:0] can be used wit
h variable latency I/O devices.
RDY/GPIO[18]
ICOCZ Variable latency I/O ready pin. (input) Notifies the memory controller
when an external bus device is ready to transfer data.
L_DD[8]/GPIO[66] ICOCZ LCD display data. (output) Transfers pixel information from the LCD
controller to the external LCD panel.
Memory controller alternate bus master request. (input) Allows an
external device to request the system bus from the memory controller.
L_DD[15]/GPIO[7
3] ICOCZ LCD display data. (output) Transfers pixel information from the LCD
controller to the external LCD panel.
Memory controller grant. (output) Notifies an external device that it
has been granted the system bus.
MBGNT/GP[13] ICOCZ
Memory controller grant.
(output) Notifies an external device that it
has been granted the system bus.
MBREQ/GP[14] ICOCZ Memory controller alternate bus master request. (input) Allows an
external device to request the system bus from the memory controller.
PCMCIA/CF Control Pins
nPOE/GPIO[48]
ICOCZ PCMCIA output enable. (output) Reads from PCMCIA memory and to
PCMCIA attribute space.
nPWE/GPIO[49] ICOCZ PCMCIA write enable. (output) Performs writes to PCMCIA memory
and to PCMCIA attribute space. Also used as the write enable signal for
variable latency I/O.
nPIOW/GPIO[51] ICOCZ PCMCIA I/O write. (output) Performs write transactions to PCMCIA
I/O space.
nPIOR/GPIO[50] ICOCZ PCMCIA I/O read. (output) Performs read transactions from PCMCIA
I/O space.