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M722 N/B MAINTENANCE
M722 N/B MAINTENANCE
3.2 Intel 82443MX Host Bridge Controller
X-bus Signal Description (1 of 4)
Signal
Type Description
BIOSCS# O
ROM BIOS Chip Selec
t. This chip select is driven active during read or write
accesses to enabled BIOS memory ranges.
DACK(3)# /
I/O
DMA Acknowledg
e. The DACK output lines indicate that a request for DMA
GPIO(28)
service has been granted by the 440MX. These lines should be used to decode
the DMA slave device with the IOR# or IOW# line to indicate selection. Upon
PCIRST#, these lines are set inactive (high). DACK3# is muxed with GPIO(28).
DACK(2:0)# O
DMA Acknowledg
e. The DACK output lines indicate that a request for DMA
service has been granted by the 440MX. These lines should be used to decode
the DMA slave device with the IOR# or IOW# line to indicate selection. Upon
PCIRST#, these lines are set inactive (high).
DREQ(3) / I/O
DMA Reques
t. The DREQ lines are used to request DMA service from the
GPIO(27) 440MX's DMA controller. All inactive to active edges of DREQ are assumed to
be asynchronous. The request must remain active until the appropriate DACKx#
signal is asserted.
DREQ3 is muxed with GPIO(27).
DREQ(2:0)
I
DMA Reques
t. The DREQ lines are used to request DMA service from the
440MX's DMA controller. All inactive to active edges of DREQ are assumed to
be asynchronous. The request must remain active until the appropriate DACKx#
signal is asserted.
IOCHRDY I/O
I/O Channel Read
y. Resources on the X-bus de-assert IOCHRDY to indicate
that additional time (wait states) is required to complete the cycle. This signal is
normally high on the X-bus.
IOR# I/O
I/O Rea
d. IOR# is the command to an X-bus I/O slave device that the slave may
drive data on to the X-bus data bus (SD[15:0]). The I/O slave device must hold
the data valid until after IOR# is negated. IOR# is driven high upon PCIRST#.
During Reset: High-Z
After Reset: High
During POS: High
IOW# I/O
I/O Writ
e. IOW# is the command to an X-bus I/O slave device that the slave
may latch data from the X-bus data bus (SD[7:0]). IOW# is driven high upon
PCIRST#.
During Reset: High-Z
After Reset: High
During POS: High
IRQ12 I
Interrupt Request 12/ Mouse Interrup
t. This pin provides a mouse interrupt
(Mouse IRQ) function. Config Dev #7, offset 4e :bit 4 in the X-bus Chip Select Register
determines the functionality of IRQ12. When bit 4=0, the standard interrupt
function is provided and this pin can be tied to the X-bus connector. When bit
Signal Type
Description
4=1, the mouse interrupt function is provided and this pin can be tied to the
IRQ12 output of the keyboard controller.
When the mouse interrupt function is selected, a low-to-high transition on this
signal is latched by the 440MX and an INT is generated to the processor as
IRQ12. An internal IRQ12 interrupt will continue to be generated until a Reset or
an I/O read access to address 60h (falling edge of IOR#) is detected. After Reset,
this pin provides the standard IRQ12 function (as an input).
IRQ8# /
I / I/O
IRQ8#
is always an active low edge-triggered interrupt input (i.e., this interrupt
GPIO(6)
cannot be modified by software). Upon PCIRST#, IRQ8# is placed in active-low
edge-sensitive mode. This signal is muxed with GPIO(6).
During Reset: High-Z
After Reset: High-Z
During Power-down: High-Z
IRQ[3:7] I
Interrupt Requests [3:7
]. The IRQ signals provide both system board
components and X-bus I/O devices with a mechanism for asynchronously
interrupting the processor. The assertion mode of these inputs depends on the
programming of the two ELCR Registers. When an ELCR bit is programmed to a
0, a low-to-high transition on the corresponding IRQ line is recognized as an
interrupt request. This "edge-triggered" mode is the 440MX default. When an
ELCR bit is programmed to a 1, a high level on the corresponding IRQ line is
recognized as an interrupt request. This mode is "level-triggered" mode.
IRQ1 I
Keyboard Interrup
t. This is the interrupt from the keyboard controller. An
(KBC IRQ) internal flip-flop is placed between the pin and the 8259 to be compatible with
keyboard controllers which only pulse IRQ1 to signal an interrupt. A low-to-high
transition on IRQ1 can be latched by the 440MX. Reads to port 60h clear the
internal flip flop, at which time the flip-flop is armed for another low-to-high
transition.
KBCCS# / O / I/O
Keyboard Chip Selec
t. KBCCS# is asserted during I/O Read or Write accesses
GPIO(26) to KBC. This signal is muxed with GPIO(26).
MCCS# / O / I/O
Microcontroller Chip Selec
t. Dedicated chip select for an external
GPIO(25)
microcontroller. The I/O registers for the microcontroller are hard coded to I/O
locations 62h and 66h.
During Reset: High
After Reset: High
During POS: High This signal is muxed with GPIO(25).
MEMR# I/O
Memory Rea
d. MEMR# is the command to a memory slave that it may drive
data onto the X-bus data bus.
During Reset: High-Z
After Reset: High
During POS: High
X-bus Signal Description (2 of 4)
