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M722 N/B MAINTENANCE
M722 N/B MAINTENANCE
3.2 Intel 82443MX Host Bridge Controller
IDE Signal Description (1 of 2)
Signal Type
Description
PDA[2:0] O
IDE Device Addres
s. These output signals are connected to the corresponding
signals on the IDE connectors. They are used to indicate which byte in either the
ATA command block or control block is being addressed.
PDCS1# O
IDE Device Chip Selects for 100 Rang
e. For ATA Command Register block.
This output signal is connected to the corresponding signal on the IDE connector.
PDCS3# O
IDE Device Chip Select for 300 Rang
e. For ATA Control Register block. This
output signal is connected to the corresponding signal on the IDE connector.
Memory I/F Signal Description ( 1 of 1)
Signal
Type
Description
CKE(3:0)# O
Clock Enable (SDRAM
). Clock Enable is used to signal a self-refresh or power-down
command to an SDRAM array when entering system Suspend. CKE is also
used to dynamically power down inactive SDRAM rows.
CS(3:0)# O
Chip Select (SDRAM).
For memory rows configured with SDRAM these pins
select the particular SDRAM components during the active state.
DQM(7:0)
O
Input/Output Data Mask (SDRAM).
These pins act as synchronized output
enables during read cycles and as a byte enables during write cycles. The read
cycles require Tdqz clock latency before the functions are performed. In the case
of write cycles, byte-masking functions are performed during the same clock
when write data is driven (i.e., 0 clock latency).
MA(13,12#, O
Memory Address (SDRAM).
MA(13,12#:11#,10,(9:0)#) signals provide the
11#, 10,
multiplexed row and column address to DRAM. Each Memory address line has a
(9:0)#)
programmable buffer strength to optimize for different signal loading conditions.
MD(63:0)
I/O
Memory Data (SDRAM).
These signals interface to the DRAM data bus.
SCAS# O
SDRAM Column Address Strobe (SDRAM).
The SCAS# signal generates
SDRAM commands encoded on SRAS#/SCAS#/WE# signals.
SRAS# O
SDRAM Row Address Strobe (SDRAM).
The SRAS# signal generates SDRAM
commands encoded on SRAS#/SCAS#/WE# signals.
WE# O
Write Enable Signal (SDRAM).
WE# is asserted during writes to DRAM. The
WE# lines have a programmable buffer strength that can be optimized for
different signal loading conditions.
INTR OD CPU Interrupt. INTR is driven by the 440MX to signal the CPU that an interrupt
request is pending and needs to be serviced. It is asynchronous with respect to
SYSCLK or PCICLK and is always an output. The interrupt controller must be
programmed following PCIRST# to ensure that INTR is at a known state.
During Reset:
Low
After Reset:
Low
During POS:
Low
NMI OD
Non-Maskable Interrup
t. NMI is used to force a non-maskable interrupt to the
processor. The 440MX can generate an NMI when either SERR# or IOCHK# is
asserted. The processor detects an NMI on a rising edge. NMI is reset by
setting the corresponding NMI source enable/disable bit in the NMI Status and
Control Register.
RCIN# I
Keyboard Controller Reset processo
r. This pin from the keyboard controller
saves the external OR gate needed. This is called RESET processor, because it
uses the KBC terminology. However, the signal is mainly used to generate INIT#.
RS(2:0)# I/O
Respons
e. Indicates type of response according to the following:
RS[2:0] Response Type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (Not driven by the 440MX)
100 Hard failure (Not driven by the 440MX)
101 No data response
110 Implicit writeback
111 Normal data response
SMI# OD
System Management Interrup
t. SMI# is an active low output synchronous to
PCICLK that is asserted by the 440MX in response to one of many enabled
hardware or software events.
Not
e: The 440MX allows synchronous SMI events to generate SMI# even after
STPCLK# has occurred.
STPCLK# OD
Stop Clock Reques
t. STPCLK# is an active low synchronous output
synchronous to PCICLK that is asserted by the 440MX in response to one of
many hardware or software events. When the processor samples STPCLK#
asserted, it responds by stopping its internal clock.
Signal Type
Description
Host Interface Signal Description (3 of 3)
