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M722 N/B MAINTENANCE
M722 N/B MAINTENANCE
3.2 Intel 82443MX Host Bridge Controller
PCI I/F Signal Description (1 of 3)
Signal
Type Description
AD[31:0] I/O
PCI Address/Dat
a. AD[31:0] is a multiplexed address and data bus. During the
first clock of a transaction, AD[31:0] contain a physical byte address (32 bits).
During subsequent clocks, AD[31:0] contain data.
C/BE[3:0]# I/O
Bus Command and Byte Enable
s. The command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used
as Byte Enables.
C/BE[3:0]# Command
Type
0 0 0 0
Interrupt Acknowledge
0 0 0 1
Special Cycle
0 0 1 0
I/O Read
0 0 1 1
I/O Write
0 1 1 0
Memory Read
0 1 1 1
Memory Write
1 0 1 0
Configuration Read
1 0 1 1
Configuration Write
1 1 0 0
Memory Read Multiple
1 1 1 0
Memory Read Line
1 1 1 1
Memory Write and Invalidate
All command encodings not shown here are Reserved. The 440MX does not use
reserved values, and does not respond if a PCI master generates a cycle using
one of the reserved values.
CLKRUN#
I/OD
PCI Clock Ru
n. CLKRUN# uses a protocol between the 440MX and various
peripherals for dynamic starting and stopping of the PCI clock.
DEVSEL# I/O
Device Selec
t. The 440MX asserts DEVSEL# to claim a PCI transaction. As an
output, the 440MX asserts DEVSEL# when it claims a PCI cycle. As an input,
DEVSEL# indicates the response to a the 440MX-initiated transaction on the PCI
bus. DEVSEL# is three-stated from the leading edge of PCIRST# and remains
three-stated by the 440MX until driven as a target.
Other System/Test Signal Description
Signal Type
Description
SPKR / O / I/O
Speake
r. The SPKR signal is the output of counter 2 and is internally "ANDed"
GPIO(14) with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external
speaker driver device. Upon PCIRST#, its output state is 0. This signal is muxed
with GPIO(14). Refer to Section 4.2 for the pin count.
TEST# I Intel Reserved signal. This signal must be strapped to an external pull-up resistor.
Signal Type
Description
PDD[15:0] I/O
IDE Device Dat
a. These signals directly drive the corresponding signals on the
IDE connector.
PDDAK#
O
IDE Device DMA Acknowledg
e. This signal directly drives the DAK# signal on
the IDE connectors. It is asserted by the 440MX to indicate to IDE DMA slave
devices that a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a
DMA data transfer cycle. This signal is used in conjunction with the PCI bus
master IDE function and is not associated with any AT-compatible DMA channel.
PDDRQ I
IDE Device DMA Reques
t. This input signal is directly driven from the DREQ
signal on the IDE connector. It is asserted by the IDE device to request a data
transfer. This signal is used in conjunction with the PCI bus master IDE function
and is not associated with any AT-compatible DMA channel.
PDIOR# O
Disk I/O Read (PIO and Non-Ultra33 DMA
). This is the command to the IDE
(PDWSTB
/
device that it may drive data onto the PDD lines. Data is latched by the 440MX
PRDMARDY
#
)
on the de-assertion edge of PDIOR#. The IDE device is selected either by the
ATA Register file chip selects (PDCS1#, PDCS3#) and the PDA lines, or the IDE
DMA acknowledge (PDDAK#).
Disk Write Strobe (Ultra33 DMA Writes to Disk). This is the data write strobe for
writes to disk. When writing to disk, the 440MX drives valid data on rising and
falling edges of PDWSTB.
Disk DMA Ready (Ultra33 DMA Reads from Disk). This is the DMA ready for
reads from disk. When reading from disk, the 440MX de-asserts PRDMARDY#
to pause burst data transfers.
PDIOW# O
Disk I/O Write (PIO and Non-Ultra33 DMA
). This is the command to the IDE
(PDSTOP) device that it may latch data from the PDD lines. The IDE device latches data on
the de-assertion edge of PDIOW#. The IDE device is selected either by the ATA
Register file chip selects (PDCS1#, PDCS3#) and the PDA lines, or the IDE DMA
acknowledge (PDDAK#).
Disk Stop (Ultra33 DMA). The 440MX asserts this signal to terminate a burst.
PIORDY I
I/O Channel Ready (PIO
). This signal keeps the strobe active (PDIOR# on
reads, PDIOW# on writes) longer than the minimum width. It adds wait states to
PIO transfers.
Disk Read Strobe (Ultra33 DMA Reads from Disk). When reading from disk, the
440MX latches data on rising and falling edges of this signal.
Disk DMA Ready (Ultra33 DMA Writes to Disk). When writing to disk, this signal
is de-asserted by the disk to pause burst data transfers.
IDE Signal Description (2 of 2)
