48
M722 N/B MAINTENANCE
M722 N/B MAINTENANCE
HIT# I/O
Hi
t. Indicates that a caching agent holds an unmodified version of the requested
line. Also driven in conjunction with HITM# by the target to extend the snoop
window.
HITM# I/O
Hit Modifie
d. Indicates that a caching agent holds a modified version of the
equested line and that this agent assumes responsibility for providing the line.
Also, driven in conjunction with HIT# to extend the snoop window.
HLOCK# I/O
Host Loc
k. All processor cycles sampled with the assertion of HLOCK# and
ADS#, until the negation of HLOCK# must be atomic, i.e., no PCI snoopable
access to DRAM is allowed when HLOCK# is asserted by the processor.
HREQ(4:0)# I/O
Request Comman
d. Asserted during both clocks of a request phase. In the first
clock, the signals define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second clock, the signals carry additional
information to define the complete transaction type. The transactions supported
by the 440MX Host Bridge are defined in Section 7.1.
HTRDY# I/O
Host Target Read
y. Indicates that the target of the processor transaction is
ready to enter the data transfer phase.
IGNNE# OD
Ignore Numeric Erro
r. This signal is connected to the ignore error pin on the
processor. IGNNE# is only used if the 440MX coprocessor error reporting
function is enabled in the XBCSA Register (bit 5=1). If FERR# is active, indicating
a coprocessor error, a write to the Coprocessor Error Register (F0h) causes the
IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If
FERR# is not asserted when the Coprocessor Error Register is written, the
IGNNE# signal is not asserted.
INIT# OD
Initialization.
INIT# is asserted in response to any one of the following
conditions:
When the System Reset bit in the Reset Control Register is reset to 0 and the
Reset CPU bit toggles from 0 to 1, the 440MX initiates a soft reset by
asserting INIT#.
* If a Shut Down Special cycle is decoded on the PCI Bus.
* If the RCIN# signal is asserted.
* If a write occurs to Port 92h, bit 0.
When asserted, INIT# remains asserted for approximately 64 PCI clocks before
being negated.
Mobile Celeron processor / Pentium II Processor:
During Reset:
High
After Reset:
High
During POS:
High
Signal Type
Description
SIGNAL DESCRIPTION
Host Interface Signal Description (1 of 3)
Signal Type
Description
A20GATE I
Address 20 Gat
e. This input from the keyboard controller is logically combined
with a bit in Port 92h which is then output via the A20M# signal. A20GATE saves
the external OR gate needed with various other chipsets.
A20M# OD
Address 20 Mas
k. A20M# goes active by either setting the appropriate bit in the
Port 92h Register, or by the A20GATE input signal.
ADS# I/O
Address Strob
e. The processor bus owner asserts ADS# to indicate the first of
two cycles of a request phase.
BNR# I/O
Block Next Reques
t. Used to block the current request bus owner from issuing
a new request. This signal is used to dynamically control the processor bus
pipeline depth.
BPRI# I/O
Priority Agent Bus Reques
t. The 440MX is the only Priority Agent on the
processor bus. The 440MX asserts this signal to obtain the ownership of the
address bus. This signal has priority over symmetric bus requests and will cause
the current symmetric owner to stop issuing new transactions unless the
HLOCK# signal was asserted.
BREQ0# I/O
Symmetric Agent Bus Reques
t. BREQ0# is asserted during CPURST# to
configure the symmetric bus agents and is negated two host clocks after
CPURST# is negated.
CPURST# I/O
CPU Rese
t. The CPURST# pin is an output from the 440MX. The 440MX
generates this signal based on the PCIRST# signal (generated internally from the
South Bridge/Cluster) and the SUS_STAT# pin. CPURST# allows the processor
to begin execution in a known state.
DBSY# I/O
Data Bus Bus
y. Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.
DEFER# I/O
Defe
r. The 440MX generates a deferred response as defined by the 440MX’s
dynamic defer policy. The 440MX also uses the DEFER# signal to indicate a
processor retry response.
DRDY# I/O
Data Read
y. Asserted for each cycle that data is transferred.
FERR# I
Numeric Coprocessor Erro
r. This signal is tied to the coprocessor error signal
on the processor. If FERR# is asserted, the 440MX generates an internal IRQ13
to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure
that IGNNE# is not asserted to the processor unless FERR# is active.
HA[31:3]# I/O
Address Bu
s. HA[31:3]# connects to the processor address bus. During
processor cycles the HA[31:3]# are inputs. Note that the address bus is inverted
on the processor bus.
HD[63:0]# I/O
Host Dat
a. These signals are connected to the processor data bus. Note that
the data signals are inverted on the processor bus.
Host Interface Signal Description (2 of 3)
3.2 Intel 82443MX Host Bridge Controller
