Midas RTE-V852-PC, Руководство пользователя

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RTE-V852-PC USER’ S MANUAL (Rev. 1.10)
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6.9. NMI STATUS PORT (3F-F160H TO 3F-F170H [READ ONLY])
This port is used to identify the source of an NMI request. See Section 9.2 for details of the NMI
signal generation logic.
Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
3F-F160H ---- ---- ---- ---- ISACOM_NMI PRT_NMI UART2_NMI UART1_NMI
3F-F170H ---- ---- ---- ---- ---- TIMER_NMI TOVER_NMI EXTBUS_NMI
Each bit is set to “ 1” when NMI is generated by the corresponding interrupt request, or set to “ 0”
when it need not be generated. Each bit represents the interrupt request status of each interrupt
request source and is not affected by the settings of the NMI enable port. Therefore, the interrupt
factor causing the NMI occurrence can be identified by ANDing the information in the NMI status port
with that in the NMI select port.
UART1_NMI: Interrupt request issued by UART-CH#1 of TL16C552A
UART2_NMI: Interrupt request issued by UART-CH#2 of TL16C552A
PRT_NMI: Interrupt request issued by PRINTER of TL16C552A
ISACOM_NMI: Interrupt request based on communication with ISA bus
EXTBUS_NMI: Interrupt request received from JEXT bus
TOVER_NMI: Interrupt request resulting from time-over ready occurrence
TIMER_NMI: Interrupt request issued by TOUT0 of
µ
PD71054
6.10. NMI/INT0/INT1 MASK PORT (3F-F180H)
This port controls the final masking of NMI, INT0 and INT1. See Section 9.2 for details of the NMI
signal generation logic and Section 9.3 for the maskable interrupt generation logic.
Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
3F-F180H ---- ---- ---- ---- ---- INT1_MASK INT0_MASK NMI_MASK
NMI_MASK: Set “ 1” to mask the NMI signal to the CPU or “ 0” when it need not be
masked.
INT0_MASK: Set “ 1” to mask the INT0(P22/INTP01) signal to the CPU or “ 0” when it need
not be masked.
INT1_MASK: Set “ 1” to mask the INT1 (P24/INTP03) signal to the CPU or “ 0” when it
need not be masked.
6.11. NMI/INT1 REQUEST CLEAR PORTS (3F-F190H, 3F-F1A0H [WRITE ONLY])
When there are latched interrupts among the NMI/INT1 request factors, these ports allow the latched
requests to be cleared.
Address Write
3F-F190H Clears the NMI/INT1 request resulting from the time-over ready
occurrence (see Section 12.1).
3F-F1A0H
Clears the NMI/INT1 request issued by TOUT0 of
µ
PD71054.