RTE-V852-PC
USER’ S MANUAL (Rev. 1.10)
50
12.2.5. Page Access (Page Mode, Same Row Address)
In the page mode cycle, continuous access to the same row address is performed by controlling only
the CAS signal while keeping the RAS signal active, as shown in the following timing chart.
•
In this timing chart, those cycles which access the same row address are generated in the
order of read, write then read, after the completion of RAS precharge of the previous cycle.
•
Zclk represents the clock count for the “ CAS Low width in read access” (see Section 6.7).
The “ CAS Low width in write access” is always one clock.
•
When the “ RAS minimum low width” (Yclk) setting is larger, by two or more, than the
“ CAS Low width in read access,” Zclk of the first cycle of the access of the same row
address becomes equal to (Yclk - 1).
•
Accessing the same row address in page mode allows the access time to be increased by at
least one wait state compared to when page mode is not used. The access speed can be
further increased if the clock count for the “ RAS precharge time” is more than two clocks.
WE-
CASn-
HIT
RAS-
Sig1: A16 to A19,UBEN-,LBEN-,R/W-
Sig1
DATA
DATA
ADDR
ADDR
ADDR
AD0 to AD15
WAIT-
ASTB
T3
T2
T1
T3
T2
T1
CLKOUT
DSTB-
Zclk
T1
T2
TW
TW
TW
TW
T3
DATA
Read Cycle
Write Cycle
Read Cycle
Zclk
