RTE-V852-PC
USER’ S MANUAL (Rev. 1.10)
28
6.3. TIC (
µ
PD71054) (3F-F030H TO 3F-F038H)
The
µ
PD71054 produced by NEC is installed as a TIC. The
µ
PD71054 is compatible with the i8254
produced by Intel. It has three timers/counters. These timers/counters are used to generate the
DRAM refresh timing and monitor timer interrupts. Each register of the TIC is assigned as listed
below.
Address
Read
Write
3F-F030H
COUNTER#0
COUNTER#0
3F-F032H
COUNTER#1
COUNTER#1
3F-F034H
COUNTER#2
COUNTER#2
3F-F036H
-----
Control Word
TIC Register Arrangement
The channels of the TIC are connected as shown in the figure below.
CH#0 is connected to the NMI generator circuit and is used as the interval timer of the monitor
program. At this time, CH#0 also functions as the prescale counter for CH#1.
CH#1 can be used as required by the user program. The status of the CH#0 and CH#1 outputs can
be read from the Status port (See Section 6.6).
CH#2 is used to generate the refresh timing. Therefore, the division value of CH#2 should be set to
30 (1EH) in mode 2.
CH#0
OUT
2 MHz
GATE
µ
PD71054
CLK
CH#1
OUT
GATE
To NMI/INT1 generator
To Status port
DRAM refresh circuit
To Status port
CLK
CH#2
OUT
GATE
CLK
RD-/WR- pulse widths of 95 ns are required to access the
µ
PD71054. As a result, wait states should
be inserted to satisfy this condition. See Section 7.4 for details of the wait setting value and Section
6.7 for details of the wait setting position.
The
µ
PD71054 requires 165 ns of command recovery time. See Section 7.5 for details of the
recovery time.
The TIC is reset when the system is reset (see Section 9.1).
