Microchip Technology MPLAB ICE, Руководство пользователя

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2001 Microchip Technology Inc. DS51159B-page 99
Advanced Features
For information on memory access selection, see Section 6.3.3. Additional
memory information that you may enter is:
• Address (Optional) – A single Event may specify one or more
addresses. This can be either a Program Memory or Data Memory
address.
• Opcode or Value (Optional) – The actual value of an opcode, the data
for a table read/write operation, or the value of a file register. Also select
whether the opcode/value is expressed as Symbolic, Binary or
Hex(adecimal).
Other triggering information that you may enter is:
• Logic Probes (Optional) – A value on the external logic probe inputs.
Also select whether the value is expressed as Binary or Hex(adecimal).
• Pass Counter – A Pass Counter counts the number of times the event
must occur before proceeding to the next event. Pass Counters are
available only with sequential trigger types (Sequential, Time Between
Events and Filter Trace).
For information on event selection, see Section 6.3.4.
Trace-related trigger information may be entered in the following dialog items:
• Trigger Position – Used to position the trigger location in the trace
memory window, indicating the number of cycles captured by the trace
memory window after the trigger occurs (Cycles Traced After Trigger).
The approximate cycle that generated the trigger will be highlighted.
• Halt On Trigger – The trigger point will generate a hardware break
point, halting the processor and will be the last entry in the trace mem-
ory window. To capture traces without halting the target, un-select this
option.
• Halt On Trace Buffer Full – A trigger will cause the trace buffer to stop
before overwriting old data. When the trace buffer is full (32767 entries),
a hardware break point will halt the processor.
Additional items on the dialog are:
• Ignore FNOP Cycles – Specifies whether or not forced NOP cycles are
to be considered in the event processing. A forced NOP cycle is the
second cycle of a two-cycle instruction. Since the PICmicro MCU archi-
tecture is pipelined, it prefetches the next instruction in the physical
address space while it is executing the current instruction. However, if
the current instruction changes the program counter, this prefetched
instruction is explicitly ignored, causing a forced NOP cycle.
Note: The number of downloaded lines specified in the Configure
Trace dialog does not affect the number of cycles collected,
and Trigger Position still applies.