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Appendix: Multi-Lane 1G IOD CDR Design

Microsemi Proprietary DG0799 Demo Guide Revision 3.0

32

To conclude, the following IOD resources are used to create an 8-lane design in a PolarFire MPF300
device:

•

One PF_IOD_CDR_CCC with a lane controller for DLL delay update

•

8 I/O Lanes and lane controllers for clock recovery

•
The following figure shows the high-level block diagram of an 8-lane design implemented using Libero
SoC PolarFire.

Figure 36 •

8 Lane 1G IOD CDR Design in PolarFire

As shown in

page 32, eight PF_IOD_CDR instances are instantiated from GPIO Banks 5 and

2 to form eight links. The clock conditioning circuit (CCC) available in the South-West corner, is
configured in the PLL-DLL cascaded mode for the clock recovery and DLL delay update.

Apart from 8 lane controllers for clock recovery, an additional lane controller from the
PF_IOD_CDR_CCC is inferred during synthesis for sharing the DLL delay update. This optimizes the
utilization of lane controllers in the device.

Board

RJ45

RJ45

RJ45

RJ45

RJ45

RJ45

RJ45

RJ45

PHY

FPGA

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

GPIO BANK 5

GPIO BANK 2

PF_IOD_CDR_0

PF_IOD_CDR_1

PF_IOD_CDR_2

PF_IOD_CDR_3

PF_IOD_CDR_4

PF_IOD_CDR_5

PF_IOD_CDR_6

PF_IOD_CDR_7

REF_CLK

PF_IOD_CDR_CCC

(SW Corner)

0°

90°

180°
270°

DLL_DELAY_CODE

TX_CLK_G_TO_CDR

RX_CLK_R

RX_CLK_R

RX_CLK_R

RX_CLK_R

RX_CLK_R

RX_CLK_R

RX_CLK_R

RX_CLK_R

LINK 1

LINK 2

LINK 3

LINK 4

LINK 5

LINK 6

LINK 7

LINK 8

DLL_DELAY_CODE

DLL_DELAY_CODE

DLL_DELAY_CODE

DLL_DELAY_CODE

DLL_DELAY_CODE

DLL_DELAY_CODE

DLL_DELAY_CODE

TX_CLK_G

TX_CLK_G

TX_CLK_G

TX_CLK_G

TX_CLK_G

TX_CLK_G

TX_CLK_G

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Содержание Microsemi PolarFire

Страница 1: ...DG0799 Demo Guide PolarFire FPGA 1G Ethernet loopback Using IO CDR...

Страница 2: ...i It is the Buyer s responsibility to independently determine suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided as is where is and...

Страница 3: ...17 3 1 Synthesize 18 3 2 Place and Route 18 3 2 1 PLL DLL and Lane Controller Placement 18 3 2 2 Resource Utilization 18 3 3 Verify Timing 18 3 4 Generate FPGA Array Data 19 3 5 Configure Design Init...

Страница 4: ...and Memories Option 20 Figure 18 Fabric RAMs Tab 20 Figure 19 Fabric RAM Tab Apply Option 21 Figure 20 Board Setup 22 Figure 21 FlashPro Express Job Project 23 Figure 22 New Job Project from FlashPro...

Страница 5: ...emo Guide Revision 3 0 v Tables Table 1 Design Requirements 2 Table 2 I O Signals 5 Table 3 Resource Utilization 18 Table 4 Jumper Settings 21 Table 5 AN Registers 34 Table 6 XCVR Configuration 34 Tab...

Страница 6: ...g is a summary of changes made in this revision Updated the document for Libero SoC v12 1 The design uses a new IP PF_IOD_CDR_CCC For more information see PF_IOD_CDR_CCC_C0 page 10 1 2 Revision 2 0 Th...

Страница 7: ...demo design which is a reference design created to demonstrate 1G Ethernet loopback using GPIO on a PolarFire Evaluation Board The demo design is built using the PF_IOD_CDR_CCC PF_IOD_CDR CoreTSE and...

Страница 8: ...sation 4 Mi V performs the following functions Executes the application from LSRAM PF_SRAM IP Configures the ZL30364 clock generation hardware through the CoreSPI IP to generate reference clocks for t...

Страница 9: ...grees for the clock recovery The recovered clock RX_CLK_R is used by the fabric for sampling the Rx data from the PF_IOD_CDR IP The CoreTSE logic also uses this clock For more information PF_IOD_CDR a...

Страница 10: ...ZL30364 and fed to NWC_PLL_0 RESET_N Input Active low Mi V reset Asserted by pressing the on board K22 push button REF_CLK_0 Input 50 MHz input clock received from the on board 50 MHz oscillator and f...

Страница 11: ...to implement the Ethernet MAC This block is configured in the ten bit interface TBI mode to interface with the VSC PHY using the SGMII interface as shown in Figure 4 page 7 The MDIO PHY Address value...

Страница 12: ...UTOCALIB_DONE signals the completion of I O calibration after which the I Os can be used Hence the AUTOCALIB_DONE and PLL_LOCK are ANDed and used to reset PF_IOD_CDR_C0_0 and CORETSE_0 This IP retains...

Страница 13: ...7FFF_FFFF Figure 5 Mi V Configurator 2 3 3 7 pf_sram_0 The pf_sram_0 block PF_SRAM_AHBL_AXI is used to access the fabric RAMs LSRAMs The pf_sram_0 is connected to Mi V as an AHB slave At device power...

Страница 14: ...PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Microsemi Proprietary DG0799 Demo Guide Revision 3 0 9 Figure 7 PF_CCC_0 Input Clock Configuration...

Страница 15: ...locks of four phases 0 90 180 270 from a 125 MHz input The CDR requires four phases of the HS_IO_CLK running at half the frequency of the serial data rate Therefore the HSIO clock frequency is selecte...

Страница 16: ...ace with ZL30364 Frame size is set to 16 to match the read write cycles supported by ZL30364 FIFO depth is set to 32 to store maximum frames TX and RX in FIFO Clock rate for the SPI master clock is se...

Страница 17: ...hows the Mi V processor bus interface memory map Figure 11 Mi V Processor Bus Interface Memory Map 2 3 3 13 CoreAHBLite_0 CoreAHBLite_0 is configured as shown in Figure 12 page 13 to interface the PF_...

Страница 18: ...DR Microsemi Proprietary DG0799 Demo Guide Revision 3 0 13 Figure 12 CoreAHBLite_0 Configuration 2 3 3 14 CoreAHBLite_2 CoreAHBLite_2 is configured as shown in Figure 13 page 14 to interface the APB p...

Страница 19: ...gure 14 page 15 to connect the peripherals CoreTSE CoreSPI and CoreUARTapb as slaves APB Master Data bus width 32 bit Number of address bits driven by master 16 The Mi V processor addresses slaves usi...

Страница 20: ...ck Using IOD CDR Microsemi Proprietary DG0799 Demo Guide Revision 3 0 15 Figure 14 CoreAPB3 Configuration 2 3 3 16 COREAHBTOAPB3_0 The COREAHBTOAPB3 IP is used to bridge between AHB and APB3 This IP r...

Страница 21: ...z On board ZL 30364 clock generation hardware This hardware generates the reference clocks for the VSC PHY the IOD CDR fabric module and CoreTSE Figure 15 page 16 shows the clocking structure of the d...

Страница 22: ...nning this demo design which includes Synthesize page 18 Place and Route page 18 Verify Timing page 18 Generate FPGA Array Data page 19 Configure Design Initialization Data and Memories page 20 Genera...

Страница 23: ...nstraint_coverage xml file for place and route constraint coverage 3 2 1 PLL DLL and Lane Controller Placement PolarFire FPGA I O pairs are grouped into lanes Each I O bank has multiple lanes Each lan...

Страница 24: ...pears next to Ver ify Timing as shown in Figure 16 page 17 2 Right click Verify Timing and select View Report to view the verify timing report and log files in the Reports tab 3 4 Generate FPGA Array...

Страница 25: ...LSRAM memory is initialized with the sNVM contents To create the LSRAM initialization client 1 On the Design Flow tab double click Configure Design Initialization Data and Memories as shown in Figure...

Страница 26: ...d select View Report to view the corresponding log file in the Reports tab 3 7 Run PROGRAM Action After generating the bitstream the PolarFire device must be programmed The programming procedure invol...

Страница 27: ...Figure 20 Board Setup 5 Power up the board using the SW3 slide switch 6 On the Libero Design Flow tab double click Run PROGRAM Action When the device is successfully programmed the LEDs 6 7 8 9 10 and...

Страница 28: ...m Installation Directory Microsemi Libero_SoC_v12 1 Designer binfp 3 Select New or New Job Project from FlashPro Express Job from Project menu to create a new job project as shown in Figure 21 page 23...

Страница 29: ...umber appears in the Programmer field If it does not confirm the board connections and click Refresh Rescan Programmers Figure 23 Programming the Device 7 Click RUN to program the device When the devi...

Страница 30: ...ed with the demo design programming file job For more information see Programming the Device Using FlashPro Express page 23 The Cat Karat and the Wireshark softwares are installed on the host PC To ru...

Страница 31: ...nection as shown in Figure 26 page 26 On a Windows 10 machine this connection is Ethernet Figure 26 Host PC Ethernet Network Connection 6 In the Cat Karat Packet Builder window Interfaces pane double...

Страница 32: ...lect the use RAW check box and set Packets per Burst to 5 and the Data Pattern to 55 as shown in Figure 28 page 27 Figure 28 Packet Flow and View Settings 8 Open the Wireshark software from the Start...

Страница 33: ...Local Area Connection and select the interface settings as shown in Figure 30 page 28 On a Window 10 machine select Ethernet Figure 30 Wireshark Interface Settings 10 Click the Start a new live captu...

Страница 34: ...e Ethernet packets transferred from the board to the host PC network card as shown in Figure 32 page 29 Figure 32 Wireshark Live Capture 11 In the Cat Karat window click Start Transmit to transmit fiv...

Страница 35: ...preceding figure highlights five packets that were transmitted from the host PC to the board looped back at the CoreTSE IP and sent back to the host PC All packets transmitted from host PC network ar...

Страница 36: ...he PF_IOD_CDR_CCC the selection of these I O Lanes must be made in any of the following ways Lanes of the same Bank can be selected vertically upto half of the side Lanes of the same Bank can be selec...

Страница 37: ...cascaded mode for the clock recovery and DLL delay update Apart from 8 lane controllers for clock recovery an additional lane controller from the PF_IOD_CDR_CCC is inferred during synthesis for shari...

Страница 38: ...see UG0677 PolarFire FPGA Transceiver User Guide This section describes how 1G Ethernet BASE T and BASE X designs are implemented in PolarFire FPGAs using the transceivers 7 1 1G Ethernet BASE T and...

Страница 39: ...0549 CoreTSE v3 1 Handbook or HB0627 CoreSGMII v3 2 Handbook The following table lists the AN registers The following registers are common in BASE T and BASE X modes Control register at address 0x00 S...

Страница 40: ...interface width 10 bits FPGA interface frequency 125 MHz PMA Mode Enabled Clocks and Resets TX clock Regional RX clock Regional PCS Reset RX Only Table 7 XCVR Port Connections Port Name Input or Outpu...

Страница 41: ...ta recovery LANE0_PCS_ARST_N Asynchronous active low reset signal used to reset the PCS module of XCVR lane LANE0_PMA_ARST_N Asynchronous active low reset signal used to reset the PMA module of XCVR l...

Страница 42: ...PolarFire FPGA Fabric User Guide For more information about CoreAHBLite see CoreAHBLite Handbook For information about COREAHBTOAPB3 see COREAHBTOAPB3 Handbook For more information about CoreAPB3 see...

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