PolarFire FPGA 1G Ethernet Loopback Using IOD CDR
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
8
2.3.3.6
Mi-V Soft Processor
The Mi-V soft processor supports RISC-V processor-based designs. The Mi-V soft processor executes
the application from the LSRAM mapped at 0x80000000. It configures the ZL30364 clock generation
hardware through the CoreSPI IP and the VSC PHY through the CoreTSE MDIO interface. It also
configures the CoreTSE registers using the AHB interface.
The following figure shows the Mi-V soft processor configuration, where the
Reset Vector Address
is
set to 0x8000_0000. This is because in the Mi-V processor memory map, the memory range used for the
AHB memory interface is 0x8000_0000 to 0x8FFF_FFFC, and the memory range used for the AHB I/O
interface is 0x6000_0000 to 0x7FFF_FFFF.
Figure 5 •
Mi-V Configurator
2.3.3.7
pf_sram_0
The pf_sram_0 block (PF_SRAM_AHBL_AXI) is used to access the fabric RAMs (LSRAMs). The
pf_sram_0 is connected to Mi-V as an AHB slave. At device power-up, the LSRAM blocks are initialized
with the user application code from sNVM.
The processor uses the SRAM memory to execute the application.
page 8 shows the LSRAM
depth and the interface settings. The
Fabric Interface type
is selected AHBLite because the fabric
interfaces with the AHB-based Mi-V processor. The memory depth can be selected based on the
application size. This design uses 64 KB of memory.
Figure 6 •
pf_sram_0 Configurator
2.3.3.8
PF_CCC_0
The PF_CCC_0 (PolarFire Clock Conditioning Circuitry) generates the fabric reference clock that drives
the soft processor and the APB peripherals (CoreTSE and CoreSPI). The PF_CCC_0 IP is configured to
generate one output fabric clock from an on-board 50 MHz crystal oscillator.
page 9 shows the PF_CCC_0 input clock configuration.
