PolarFire FPGA 1G Ethernet Loopback Using IOD CDR
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
10
page 10 shows the PF_CCC_0 output clock configuration. This design uses an 80-MHz system
clock for configuring the APB peripherals.
Figure 8 •
PF_CCC_0 Output Clock Configuration
2.3.3.9
PF_IOD_CDR_CCC_C0
The PF_IOD_CDR_CCC IP used for generating high-speed bank clocks for PF_IOD_CDR. This IP is in
PLL-DLL cascaded mode to generate high-speed bank clocks of four phases 0, 90, 180, 270 from a 125
MHz input. The CDR requires four phases of the HS_IO_CLK running at half the frequency of the serial
data rate. Therefore, the HSIO clock frequency is selected as 625 MHz with four phases.
PF_IOD_CDR_CCC also generates the fabric Tx interface clock (TX_CLK_G) for the CoreTSE block by
dividing the bank clock by the ratio of 5. The DLL is needed to control the clock position (delay) with DLL
codes when the data is active on the Rx interface (RX_P/RX_N). A glitch-less DLL can adjust the clock
delay setting when the data is active.
page 10 shows the PF_IOD_CCC_C0_0 configuration.
Figure 9 •
PF_IOD_CDR_CCC Configuration
