6.
Appendix
6.1
Schematics
Figure 6-1. AVR-BLE Target schematic
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
D
D
C
C
B
B
A
A
2
of
5
A
V
R
-B
L
E
2020
-01-09
A
V
R
-B
LE
_T
ar
ge
t_
M
C
U
.S
ch
D
oc
Pr
oj
ec
t T
itle
PC
B
A
ss
em
bl
y
N
um
ber:
PC
B
A
R
ev
is
ion:
Fil
e:
P
C
B
N
um
be
r:
P
C
B
R
ev
ision:
De
sig
n
ed
w
it
h
D
ra
w
n
B
y:
M
ic
ro
ch
ip
N
or
w
ay
Sh
ee
t T
itle
Ta
rg
et
M
C
U
E
ng
ineer:
T
F
A
08-3038
2
Size
A
3
A
09-3314
3
Pa
ge
:
Date:
A
lti
um
.c
om
GND
100n
C200
1k
R210
U
S
E
R
L
E
D
S
V
C
C
_T
A
RGET
PF
3_S
W0_
DG
I_F
W
U
S
E
R
B
U
T
T
O
N
D
B
G
0
C
D
C
_
U
A
R
T
TX
RX
U
A
R
T
D
B
G
1
D
B
G
2
218
5-1
08S
S0C
YN
P1
1
2
3
4
5
6
7
8
J200
218
5-1
08S
S0C
YN
P1
1
2
3
4
5
6
7
8
J201
m
ik
ro
B
U
S
GND
GND
A
N
R
ST
C
S
SCK
M
IS
O
M
O
SI
+3.
3V
GND
PWM
INT
RX
TX
SC
L
SD
A
+
5V
GND
H
ea
d
er
(F
em
al
e)
T
M
RN4870
10uF/10V
C202
10nF
C201
330
R
R20
7
1
2
4
3
5
KM
R22
1G
SW200
1k
R209
1k
R208
GND
S
D
A
5
S
C
L
6
G
N
D
4
V
C
C
8
P
A
D
9
N
C
1
N
C
2
N
C
3
N
C
7
U2
01
G
ND
G
ND
100
k
R20
1
V
C
C
_T
A
RGET
V
C
C
_T
A
RGET
PA
3_
I2
C
_S
C
L
PA
2_
I2
C
_S
D
A
V
C
C
_T
A
RGET
G
ND
100n
C204
C
ry
p
to
A
u
th
en
ti
ca
ti
on
T
M
T
em
p
er
at
u
re
Se
n
so
r
GND
V
C
C
_T
A
RGET
4.7
k
R20
4
4.7
k
R20
5
V
C
C
_T
A
RGET
V
C
C
_T
A
RGET
T
P2
11
TP203
TP210
TP212
TP208
2
1
G
R
E
E
N
L
ED
SM
L
-P12MTT86R
D200
R
E
D
L
ED
SM
L
-P12VTT86R
2
1
D201
D
ef
au
lt
I
2C
a
dd
re
ss
: 0
x1
8
P
D
5_
M
B
U
S
_R
ST
PA
3_I
2C
_SC
L
PA
2_I
2C
_SD
A
P
D
7_
M
B
U
S
_A
IN
P
D
6_
M
B
U
S
_I
N
T
D
ef
au
lt
I
2C
a
dd
re
ss
: 0
x5
8
2
1
B
L
U
E
L
ED
SM
L
P13
BC8TT86
D20
2
V
C
C
_T
A
RGET
GN
D
PC
0_
U
A
R
T
1_TX
PC
1_
U
A
R
T1_RX
TP214
100n
C205
SW
0
V
B
U
S
0R
R206
+
5V
TP213
TP209
D
A
TA
A
T
E
C
C
60
8A
D
B
G
3
PA
3_I
2C
_SC
L
PA
2_I
2C
_SD
A
V
C
C
_T
A
RGET
PD
2_
B
L
E
_R
X
_I
ND
10k
R20
0
N
.M
.
3-
ax
ia
l A
cc
el
er
at
io
n
S
en
sor
V
C
C
_T
A
RGET
G
ND
100
n
C20
6
G
ND
100
n
C20
7
G
ND
A
lt
er
na
te
I2
C
a
dd
re
ss
: 0
x1
9
V
C
C
_T
A
RGET
PA
3_I
2C
_SC
L
PA
2_I
2C
_SD
A
1uF
C203
G
ND
A
T
meg
a320
8
PC
2_
A
C
C
L
_I
NT1
MCP9844
S
D
A
5
S
C
L
6
E
V
E
N
T
7
G
N
D
4
A
2
3
A
1
2
A
0
1
V
D
D
8
E
P
9
U202
PA
5_
SP
I_
M
IS
O
PA
6_
SP
I_
SCK
PA
4_
SP
I_
M
O
SI
PA
7_
SP
I_
C
S
S
D
O
/
A
S
E
L
1
S
D
x
2
V
D
D
I
O
3
N
C
4
IN
T1
5
IN
T2
6
V
D
D
7
G
N
D
I
O
8
G
N
D
9
C
S
B
1
0
PS
11
SC
x
12
B
M
A
253
U203
51
2k
x
8
S
er
ia
l F
la
sh
V
C
C
_T
A
RGET
G
ND
100n
C208
G
ND
V
C
C
_T
A
RGET
PF
5_E
RR
_L
ED
P
D
1_
M
B
U
S_PWM
PF
4_D
A TA
_L
ED
_D
GI
B
L
E
ERR
PF
3_
SW
0_
D
G
I_FW
TP201
PD
0_S
PI_
CS
PA
5_S
PI_
MIS
O
PA
6_S
PI_
SC
K
PA
4_S
PI_
MO
SI
V
C
C
_T
A
RGET
TP207
TP206
TP202
TP204
TP205
P
A
3
1
(E
XT
CL
K)
PA
0
30
PA
1
31
PA
2
32
P
A
4
2
P
A
5
3
P
A
6
4
P
A
7
5
P
C
0
6
P
C
1
7
P
C
2
8
PC
3
9
PD
0
10
PD
1
11
PD
2
12
PD
3
13
PD
4
14
PD
5
15
PD
6
16
P
D
7
1
7
A
V
D
D
1
8
G
N
D
1
9
(
T
O
S
C
1
)
P
F
0
2
0
(
T
O
S
C
2
)
P
F
1
2
1
P
F
2
2
2
P
F
3
2
3
P
F
4
2
4
PF
5
25
PF
6
26
UP
DI
27
VD
D
28
GN
D
29
P
A
D
3
3
A
T
m
eg
a3208-MFR
U2
00
10k
R21
2
PF
6_R
ST
PA
7_
SP
I_
C
S
PA
6_
SP
I_
SCK
PA
5_
SP
I_
M
IS
O
PA
4_
SP
I_
M
O
SI
G
ND
P
F
1_
C
D
C
_U
A
R
T2_RX
PF
4_
D
A
TA
_L
E
D
_D
G
I
P
D
7_
M
B
U
S_
A
IN
P
F
0_
C
D
C
_U
A
R
T2_TX
PA
3_
I2
C
_S
C
L
PF
3_
SW
0_
D
G
I_FW
P
D
5_
M
B
U
S_
R
ST
P
D
4_
H
O
L
D#
PD
3_
B
L
E
_R
ST
PD
0_
SP
I_
C
S
PD
2_
B
L
E
_R
X
_I
ND
P
D
6_
M
B
U
S_
INT
PA
2_I
2C
_SD
A
PA
0_B
LE
_U
AR
T0_
TX
PA
1_B
LE
_U
AR
T0_
RX
PA
1_
B
L
E
_U
A
R
T0_RX
PA
0_
B
L
E
_U
A
R
T
0_TX
UP
DI
PF
5_E
RR
_L
ED
BL
E_L
ED
B
L
E
_L
E
D
PF2_EVENT
PF
2_E
VE
NT
PC
0_
U
A
R
T1_TX
PC
1_
U
A
R
T1_RX
PC
2_
A
C
C
L
_I
NT1
PD
3_
B
L
E
_R
ST
V
C
C
_T
A
RGET
PC
3_
A
C
C
L
_I
NT2
PC
3_
A
C
C
L
_I
NT2
PD
4_H
OL
D#
P
D
1_
M
B
U
S_PWM
10k
R20
2
C
E
#
1
S
O
/
S
I
O
1
2
W
P
#
3
V
S
S
4
V
D
D
8
H
O
L
D
#
7
S
C
K
6
S
I
/
S
I
O
0
5
SS
T
25
PF
04
0C
T
-4
0I
/NP
U204
P
2_
0/
M
O
D
E
p
in
h
as
a
n
in
te
rn
al
p
ul
l-
up
o
f
ab
ou
t
50
ko
hm
.
U
PD
I
PF
6_
R
ST
10
k
R
21
1
V
C
C
_T
A
RGET
PC
2_
A
C
C
L
_I
NT1
0R
R203
0R
R213
V
D
D
3
V
O
U
T
1
V
S
S
2
M
C
P1
11
T
-195
U20
5
N
.M
.
GN
D
V
C
C
_T
A
RGET
R
T
S
C
T
S
P02
P07
P12
P13
P27
P35
PCO
BKO
PF
3_
SW
0_
D
G
I_FW
PF
4_
D
A
TA
_L
E
D
_D
G
I
RN4870_TX
RN4870_RX
C
ro
ss
in
g RX
/TX here!
RN4870_RX
RN4870_TX
PF
3_
SW
0_
D
G
I_FW
100n
C209
GN
D
GN
D
M
ak
e
su
re
th
at
th
e
C
D
C
U
A
R
T
p
in
s
ar
e
no
t u
se
d
(d
ri
ve
n
hi
gh) w
hen operat
ing
in
ba
tt
er
y m
od
e
to
av
oid
po
w
er
in
g
the debugg
er
th
ro
ug
h its I/
O
p
in
s
(c
au
si
ng
le
ak
ag
e
fr
om
V
C
C
_T
A
R
G
E
T
t
o
V
C
C_
D
EB
U
G
GE
R
).
G
N
D
1
G
N
D
2
G
N
D
3
V
B
A
T
4
P
2_
2
5
V
D
D
_I
O
6
V
D
D
_I
O
7
U
L
P
C
_O
8
P
2_
3
9
B
K
_O
10
P
1_
1
12
P
1_
0
16
P
3_
6/
R
T
S
17
P
2_
0/
M
O
D
E
18
P
2_
4
19
N
C
20
R
S
T
21
U
A
R
T
_R
X
22
U
A
R
T
_T
X
23
P
3_
1
24
P
3_
2
25
P
3_
3
26
P
3_
4
27
P
3_
5
28
P
0_
7
29
P
0_
2
30
G
N
D
31
G
N
D
32
G
N
D
33
P
2_
7/
T
X
_I
N
D
11
P
1_
2/
S
C
L
13
P
1_
3/
SD
A
14
P
0_
0/
C
T
S
15
RN4870-V/RM140
M
20
0
Appendix
©
2020 Microchip Technology Inc.
User Guide
DS50002956A-page 24