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Organization of the Board
MEN Mikro Elektronik GmbH
85
20G020-00 E5 – 2014-01-21
4
Organization of the Board
4.1
SMBus Devices
Table 18.
SMBus devices
4.2
PCI Express Root Port Interrupt Mapping
Table 19.
PCI Express Root Port Interrupt Mapping for Downstream Devices
Function
SMB Address
SMB Address
1
(Hex)
1
The first address is for write command, the second for read command
Clock generator
1101 001x
0xD2 / 0xD3
SPD EEPROM
(memory channel A)
1010 000x
0xA0
SPD EEPROM
(memory channel B)
1010 010x
0xA4
Board EEPROM
1001 111x
0xAE
Protected register
0110 010x
0x6E
Temperature sensor
0011 010x
0x3E
Port
INTA#
INTB# INTC# INTD#
1 INTA# INTB#
INTC#
INTD#
2 INTB#
INTC# INTD#
INTA#
3
INTC# INTD#
INTA#
INTB#
4
INTD#
INTA# INTB#
INTC#
5
INTA# INTB#
INTC#
INTD#
6
INTB#
INTC# INTD#
INTA#
7
INTC# INTD#
INTA#
INTB#
8
INTD#
INTA# INTB#
INTC#