MT3620
Hardware User Guide
MediaTek Confidential
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2020 MediaTek Inc.
Page 21 of 40
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8
Power Rails
MT3620 requires a regulated 3.3V power supply, for example from a DC-DC converter, to convert
whatever source voltage rail is used to 3.3V.
The MT3620 power management unit (PMU) contains an under-voltage lockout (UVLO) circuit, low
drop-out regulators (LDOs), a highly efficient buck converter, a reference band-gap circuit and a voltage
comparator for brown-out detection. These circuits are optimized for low quiescent current, low drop-
out voltage, good line/load regulation, good ripple rejection and low output noise.
8.1
MT3620 PMU Architecture
The PMU integrates one buck converter and three LDOs: CLDO, ALDO, ELDO (CLDO: digital core LDO,
ALDO: ADC LDO, ELDO: e-fuse LDO).
The buck DC-DC converter generates a 1.6V output to power other MT3620 sub-systems. Through an
external LC filter (based on a 2.2uH inductor and a 10uF capacitor), it outputs a low ripple 1.6V for the
Wi-Fi RF system, and CLDO. The CLDO generates 1.15V for the whole chip digital circuit from the 1.6V
buck-converted domain.
For ADC requirements, the ALDO is integrated to generate 2.5V from the 3.3V chip supply. By default,
the ALDO is off after power-on. It should be enabled before use and disabled it when not in use to save
power.
The ELDO (e-fuse LDO) is also integrated into the PMU. It provides a 2.5V output voltage for the e-fuse
logic and supports 60mA of maximum operation current. The ELDO is automatically and dynamically
enabled and disabled by the e-fuse controller. It is not necessary to enable/disable it in software.
BUCK
(3.3V)
CLDO
(1.6V)
AVDD_3V3_BUCK
PMU_CAP
VO UT_1V15
DVDD_1V15
AVDD_1V6_CLDO
VO UT_1V6
DVDD_3V3
AVDD_1V6_WF_TRX
AVDD_1V6_WF_AFE
AVDD_1V6_XO
RF LDO/RF
core (1.6V)
IO (3.3V)
AVDD_3V3_WF_A_TX
AVDD_3V3_WF_A_PA
AVDD_3V3_WF_G_TX
AVDD_3V3_WF_G_PA
RF(3.3V)
1V6
1V15
3V3
Digital core
(1.15V)
AVSS_3V3_BUCK
VSS
VOUT_2V5
ALDO
(3.3V)
ADC
(2.5V)
AVDD_2V5_ADC
ELDO
(3.3V to 2.5V)
AVSS_2V5_ADC
VSS
VSS
2V5
Figure 8-1 Chip Power Block Diagram
