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DS3232

Control/Status Register (0Fh)

Bit 7: Oscillator Stop Flag (OSF). 

A logic 1 in this bit

indicates that the oscillator either is stopped or was
stopped for some period and may be used to judge the
validity of the timekeeping data. This bit is set to logic 1
any time that the oscillator stops. The following are
examples of conditions that can cause the OSF bit to
be set:

1) The first time power is applied.

2) The voltages present on both V

CC

and V

BAT

are

insufficient to support oscillation.

3) The 

EOSC

bit is turned off in battery-backed mode.

4) External influences on the crystal (i.e., noise, leak-

age, etc.).

This bit remains at logic 1 until written to logic 0.

Bit 6: Battery-Backed 32kHz Output (BB32kHz).

This

bit enables the 32kHz output when powered from V

BAT

(provided EN32kHz is enabled). If BB32kHz = 0, the
32kHz output is low when the part is powered by V

BAT

.

Bits 5 and 4: Conversion Rate (CRATE1 and
CRATE0). 

These two bits control the sample rate of the

TCXO. The sample rate determines how often the tem-
perature sensor makes a conversion and applies com-
pensation to the oscillator. Decreasing the sample rate
decreases the overall power consumption by decreas-
ing the frequency at which the temperature sensor
operates. However, significant temperature changes
that occur between samples may not be completely
compensated for, which reduce overall accuracy.
When a new conversion rate is written to the register, it
may take up to the new conversion rate time before the
conversions occur at the new rate.

Bit 3: Enable 32kHz Output (EN32kHz).

This bit indi-

cates the status of the 32kHz pin. When set to logic 1,
the 32kHz pin is enabled and outputs a 32.768kHz
square-wave signal. When set to logic 0, the 32kHz pin
goes low. The initial power-up state of this bit is logic 1,
and a 32.768kHz square-wave signal appears at the
32kHz pin after a power source is applied to the DS3232
(if the oscillator is running).

Bit 2: Busy (BSY).

This bit indicates the device is busy

executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the conversion is complete.

Bit 1: Alarm 2 Flag (A2F).

A logic 1 in the alarm 2 flag

bit indicates that the time matched the alarm 2 regis-
ters. If the A2IE bit is logic 1 and the INTCN bit is set to
logic 1, the 

INT

/SQW pin is also asserted. A2F is

cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.

Bit 0: Alarm 1 Flag (A1F).

A logic 1 in the alarm 1 flag

bit indicates that the time matched the alarm 1 regis-
ters. If the A1IE bit is logic 1 and the INTCN bit is set to
logic 1, the 

INT

/SQW pin is also asserted. A1F is

cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.

Extremely Accurate I

2

C RTC with 

Integrated Crystal and SRAM

14

____________________________________________________________________

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

NAME:

OSF

BB32kHz

CRATE1

CRATE0

EN32kHz

BSY

A2F

A1F

POR*:

1

1

0

0

1

0

0

0

Control/Status Register (0Fh)

*

POR is defined as the first application of power to the device, either V

BAT

or V

CC

.

CRATE1

CRATE0

SAMPLE RATE

(seconds)

0

0

64

0

1

128

1

0

256

1

1

512

Содержание Maxim DS3232 Series

Страница 1: ...atures Accuracy 2ppm from 0 C to 40 C Accuracy 3 5ppm from 40 C to 85 C Battery Backup Input for Continuous Timekeeping Operating Temperature Ranges Commercial 0 C to 70 C Industrial 40 C to 85 C 236...

Страница 2: ...ard Layout and Assembly section PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC 2 3 3 3 5 5 Supply Voltage VBAT 2 3 3 0 5 5 V Logic 1 Input SDA SCL VIH 0 7 x VCC VCC 0 3 V Logic 0 Input SDA SCL VIL...

Страница 3: ...63 31 69 0 C to 40 C 2 2 Frequency Stability vs Temperature f fOUT VCC 3 3V or VBAT 3 3V 40 C to 0 C and 40 C to 85 C 3 5 3 5 ppm Frequency Stability vs Voltage f V VCC 3 3V or VBAT 3 3V 1 ppm V 40 C...

Страница 4: ...de 100 Data Setup Time Note 10 tSU DAT Standard mode 250 ns Fast mode 0 6 Start Setup Time tSU STA Standard mode 4 7 s Fast mode 300 Rise Time of Both SDA and SCL Signals Note 11 tR Standard mode 20 0...

Страница 5: ...te I2C RTC with Integrated Crystal and SRAM _____________________________________________________________________ 5 Pushbutton Reset Timing tRST PBDB RST Power Switch Timing VCC VPF MAX RST VPF MIN tV...

Страница 6: ...of the falling edge of SCL Note 9 The maximum tHD DAT needs only to be met if the device does not stretch the low period tLOW of the SCL signal Note 10 A fast mode device can be used in a standard mod...

Страница 7: ...DS3232 toc03 TEMPERATURE C SUPPLY CURRENT A 80 60 40 20 0 20 0 700 0 800 0 900 0 600 40 VCC 0V BB32kHz 0 VBAT 3 4V VBAT 3 0V FREQUENCY DEVIATION vs TEMPERATURE vs AGING DS3232 toc04 TEMPERATURE C FREQ...

Страница 8: ...and accurate reference clock and maintains the RTC to within 2 minutes per year accu racy from 40 C to 85 C The TCXO frequency output is available at the 32kHz pin The RTC is a low power clock calend...

Страница 9: ...t When using the device with the VBAT input as the primary power source this pin should be decoupled using a 0 1 F to 1 0 F low leakage capacitor When using the device with the VBAT input as the backu...

Страница 10: ...ising edge Upon detecting release the DS3232 forces the RST pin low and holds it low for tRST The same pin RST is used to indicate a power fail con dition When VCC is lower than VPF an internal power...

Страница 11: ...RAM ____________________________________________________________________ 11 Figure 1 Address Map for DS3232 Timekeeping Registers and SRAM Note Unless otherwise specified the registers state is not de...

Страница 12: ...ch of the time of day date alarm registers are mask bits Table 2 When all the mask bits for each alarm are logic 0 an alarm only occurs when the values in the timekeeping registers match the correspon...

Страница 13: ...e bits control the frequency of the square wave output when the square wave has been enabled The following table shows the square wave frequencies that can be select ed with the RS bits These bits are...

Страница 14: ...Output EN32kHz This bit indi cates the status of the 32kHz pin When set to logic 1 the 32kHz pin is enabled and outputs a 32 768kHz square wave signal When set to logic 0 the 32kHz pin goes low The in...

Страница 15: ...s section for a graph showing the effect of the register on accu racy over temperature Temperature Registers 11h 12h Temperature is represented as a 10 bit code with a res olution of 0 25 C and is acc...

Страница 16: ...clock signal The data on the line must be changed during the low period of the clock signal There is one clock pulse per bit of data Each data transfer is initiated with a START condition and terminat...

Страница 17: ...___________________________________________________ 17 A XXXXXXXX A 1101000 S 0 XXXXXXXX A XXXXXXXX A XXXXXXXX A P R W WORD ADDRESS n DATA n DATA n 1 DATA n X S START A ACKNOWLEDGE ACK P STOP R W READ...

Страница 18: ...are after reception of the slave address and direction bit The slave address byte is the first byte received after the master generates a START condition The slave address byte contains the 7 bit DS32...

Страница 19: ...ower is applied and the oscillator is disabled 9 Added a paragraph to the Pushbutton Reset Function section about how the RST output operation does not affect the device s internal operation 10 3 10 0...

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