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Special-Purpose Registers

The DS3232 has two additional registers (control and
control/status) that control the real-time clock, alarms,
and square-wave output.

Control Register (0Eh)

Bit 7: Enable Oscillator (

EOSC

). 

When set to logic 0,

the oscillator is started. When set to logic 1, the oscilla-
tor is stopped when the DS3232 switches to battery
power. This bit is clear (logic 0) when power is first
applied. When the DS3232 is powered by V

CC

, the

oscillator is always on regardless of the status of the

EOSC

bit. When 

EOSC

is disabled, all register data is

static.

Bit 6: Battery-Backed Square-Wave Enable
(BBSQW). 

When set to logic 1 with INTCN = 0 and V

CC

< V

PF

, this bit enables the square wave. When BBSQW

is logic 0, the 

INT

/SQW pin goes high impedance when

V

CC

< V

PF

. This bit is disabled (logic 0) when power is

first applied.

Bit 5: Convert Temperature (CONV). 

Setting this bit to

1 forces the temperature sensor to convert the temper-
ature into digital code and execute the TCXO algorithm
to update the capacitance array to the oscillator. This
can only happen when a conversion is not already in
progress. The user should check the status bit BSY
before forcing the controller to start a new TCXO exe-
cution. A user-initiated temperature conversion does
not affect the internal 64-second (default interval)
update cycle.

A user-initiated temperature conversion does not affect
the BSY bit for approximately 2ms. The CONV bit
remains at a 1 from the time it is written until the conver-
sion is finished, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring
the status of a user-initiated conversion.

Bits 4 and 3: Rate Select (RS2 and RS1). 

These bits

control the frequency of the square-wave output when

the square wave has been enabled. The following table
shows the square-wave frequencies that can be select-
ed with the RS bits. These bits are both set to logic 1
(8.192kHz) when power is first applied.

Bit 2: Interrupt Control (INTCN). 

This bit controls the

INT

/SQW signal. When the INTCN bit is set to logic 0, a

square wave is output on the 

INT

/SQW pin. When the

INTCN bit is set to logic 1, a match between the time-
keeping registers and either of the alarm registers acti-
vates the 

INT

/SQW (if the alarm is also enabled). The

corresponding alarm flag is always set regardless of
the state of the INTCN bit. The INTCN bit is set to logic
1 when power is first applied.

Bit 1: Alarm 2 Interrupt Enable (A2IE).

When set to

logic 1, this bit permits the alarm 2 flag (A2F) bit in the
status register to assert 

INT

/SQW (when INTCN = 1).

When the A2IE bit is set to logic 0 or INTCN is set to
logic 0, the A2F bit does not initiate an interrupt signal.
The A2IE bit is disabled (logic 0) when power is first
applied.

Bit 0: Alarm 1 Interrupt Enable (A1IE).

When set to

logic 1, this bit permits the alarm 1 flag (A1F) bit in the
status register to assert 

INT

/SQW (when INTCN = 1).

When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the 

INT

/SQW sig-

nal. The A1IE bit is disabled (logic 0) when power is
first applied.

DS3232

Extremely Accurate I

2

C RTC with 

Integrated Crystal and SRAM

____________________________________________________________________

13

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

NAME:

EOSC

BBSQW

CONV

RS2

RS1

INTCN

A2IE

A1IE

POR*:

0

0

0

1

1

1

0

0

RS2

RS1

SQUARE-WAVE OUTPUT

FREQUENCY

0

0

1Hz

0

1

1.024kHz

1

0

4.096kHz

1

1

8.192kHz

SQUARE-WAVE OUTPUT FREQUENCY

Control Register (0Eh)

*

POR is defined as the first application of power to the device, either V

BAT

or V

CC

.

Содержание Maxim DS3232 Series

Страница 1: ...atures Accuracy 2ppm from 0 C to 40 C Accuracy 3 5ppm from 40 C to 85 C Battery Backup Input for Continuous Timekeeping Operating Temperature Ranges Commercial 0 C to 70 C Industrial 40 C to 85 C 236...

Страница 2: ...ard Layout and Assembly section PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC 2 3 3 3 5 5 Supply Voltage VBAT 2 3 3 0 5 5 V Logic 1 Input SDA SCL VIH 0 7 x VCC VCC 0 3 V Logic 0 Input SDA SCL VIL...

Страница 3: ...63 31 69 0 C to 40 C 2 2 Frequency Stability vs Temperature f fOUT VCC 3 3V or VBAT 3 3V 40 C to 0 C and 40 C to 85 C 3 5 3 5 ppm Frequency Stability vs Voltage f V VCC 3 3V or VBAT 3 3V 1 ppm V 40 C...

Страница 4: ...de 100 Data Setup Time Note 10 tSU DAT Standard mode 250 ns Fast mode 0 6 Start Setup Time tSU STA Standard mode 4 7 s Fast mode 300 Rise Time of Both SDA and SCL Signals Note 11 tR Standard mode 20 0...

Страница 5: ...te I2C RTC with Integrated Crystal and SRAM _____________________________________________________________________ 5 Pushbutton Reset Timing tRST PBDB RST Power Switch Timing VCC VPF MAX RST VPF MIN tV...

Страница 6: ...of the falling edge of SCL Note 9 The maximum tHD DAT needs only to be met if the device does not stretch the low period tLOW of the SCL signal Note 10 A fast mode device can be used in a standard mod...

Страница 7: ...DS3232 toc03 TEMPERATURE C SUPPLY CURRENT A 80 60 40 20 0 20 0 700 0 800 0 900 0 600 40 VCC 0V BB32kHz 0 VBAT 3 4V VBAT 3 0V FREQUENCY DEVIATION vs TEMPERATURE vs AGING DS3232 toc04 TEMPERATURE C FREQ...

Страница 8: ...and accurate reference clock and maintains the RTC to within 2 minutes per year accu racy from 40 C to 85 C The TCXO frequency output is available at the 32kHz pin The RTC is a low power clock calend...

Страница 9: ...t When using the device with the VBAT input as the primary power source this pin should be decoupled using a 0 1 F to 1 0 F low leakage capacitor When using the device with the VBAT input as the backu...

Страница 10: ...ising edge Upon detecting release the DS3232 forces the RST pin low and holds it low for tRST The same pin RST is used to indicate a power fail con dition When VCC is lower than VPF an internal power...

Страница 11: ...RAM ____________________________________________________________________ 11 Figure 1 Address Map for DS3232 Timekeeping Registers and SRAM Note Unless otherwise specified the registers state is not de...

Страница 12: ...ch of the time of day date alarm registers are mask bits Table 2 When all the mask bits for each alarm are logic 0 an alarm only occurs when the values in the timekeeping registers match the correspon...

Страница 13: ...e bits control the frequency of the square wave output when the square wave has been enabled The following table shows the square wave frequencies that can be select ed with the RS bits These bits are...

Страница 14: ...Output EN32kHz This bit indi cates the status of the 32kHz pin When set to logic 1 the 32kHz pin is enabled and outputs a 32 768kHz square wave signal When set to logic 0 the 32kHz pin goes low The in...

Страница 15: ...s section for a graph showing the effect of the register on accu racy over temperature Temperature Registers 11h 12h Temperature is represented as a 10 bit code with a res olution of 0 25 C and is acc...

Страница 16: ...clock signal The data on the line must be changed during the low period of the clock signal There is one clock pulse per bit of data Each data transfer is initiated with a START condition and terminat...

Страница 17: ...___________________________________________________ 17 A XXXXXXXX A 1101000 S 0 XXXXXXXX A XXXXXXXX A XXXXXXXX A P R W WORD ADDRESS n DATA n DATA n 1 DATA n X S START A ACKNOWLEDGE ACK P STOP R W READ...

Страница 18: ...are after reception of the slave address and direction bit The slave address byte is the first byte received after the master generates a START condition The slave address byte contains the 7 bit DS32...

Страница 19: ...ower is applied and the oscillator is disabled 9 Added a paragraph to the Pushbutton Reset Function section about how the RST output operation does not affect the device s internal operation 10 3 10 0...

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