6
MAX3421E Programming Guide
Resets
The MAX3421E has three reset sources:
1. An internal Power-On-Reset (POR) circuit
2. A RES# pin
3. A register bit called CHIPRES
There is a fourth way in which a reset can occur. When the HOST bit changes state (switching to
host or peripheral operation), the SIE clears certain register bits.
The following section explains the effect of each reset source.
MAX3421E register bits are clocked from two sources:
1. The internal 12MHz oscillator
2. The SCLK signal that the CPU supplies to the SPI interface.
Asserting the RES# or PWRDOWN reset stops the internal 12MH clock. Most register bits are
asynchronously cleared. However, the register bits that are clocked from the SPI interface remain
active so the CPU can control the SPI configuration (e.g., the FDUPSPI bit), USB bus pulldown
resistors, and the state of the PWRDOWN bit.
Power-On Reset
The SIE clears every register bit. Once out of reset, the SIE sets the following bits to indicate
available buffers:
•
IN3BAVIRQ (peripheral)
•
IN2BAVIRQ (peripheral)
•
IN0BAVIRQ (peripheral)
•
SNDBAVIRQ (host)
Note
: POR sets HOST = 0, defaulting to peripheral operation.
Asserting the RES# Pin or Setting CHIPRES = 1
These resets stop the internal 12MHz oscillator and clear most register bits, but leave the SPI-
clocked register bits undisturbed and still accessible by the CPU. The SPI-clocked register bits
are:
•
HOSCSTEN
•
VBGATE
•
CHIPRES
•
PWRDOWN
•
CONNECT
•
SIGRWU
•
FDUPSPI