Maxim MAX3421E, Руководство по программированию, Страница: 42 / 63

42
MAX3421E Programming Guide
Programming Notes
Clear first IRQ,
second IRQ
still active
INTLEVEL=1
POSINT=X
First IRQ
Active
Second IRQ
Active
Clear last
pending IRQ
Single
IRQ
Clear
IRQ
(1)
(2)
(1) Width determined by clearing the IRQ. Width determined by PULSEWID[1:0].
INTLEVEL=0
POSINT=X
INTLEVEL=0
POSINT=X
Figure 8. INT pin behavior depending on INTLEVEL and POSINT bits
.
The waveforms in
Figure 8
show the INT pin behavior for different settings of the INTLEVEL
and POSINT bits.
In level mode (top diagram) the INT pin stays low until no interrupt requests are pending. The
INTLEVEL mode is open-drain and requires a pullup resistor from the INT pin to VL.
In edge mode the INT pin delivers an edge whenever a new interrupt request occurs or an
interrupt request bit is cleared while others are pending. If an interrupt is pending when another
is cleared in edge mode, the INT pin momentarily goes inactive, then active again to deliver the
edge. The inactive time, shown as (2) in the
Figure 8
, is programmable to four values, shown in
the table below.
PULSEWID1 PULSEWID0
INT Pulse
Width uS
0 0 10.6
0 1 5.3
1 0 2.6
1 1 1.3
Note: The MAX3420E does not have the PULSEWID[1:0] bits. The MAX3420E time is fixed at
10.6 μ S.
When
SEPIRQ = 1, the MAX3421E removes the eight interrupts associated with the eight GPIN
pins from the INT pin. The MAX3421E then routes them to the GPX pin, which serves as a
second interrupt output pin when GPX[B:A] = 10. When the GPX pin operates in this manner its
characteristics as an INT output pin are set by the INTLEVEL, POSINT, and PULSEWID[1:0]
bits.