Maxim MAX3421E, Руководство по программированию, Страница: 28 / 63

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MAX3421E Programming Guide
The SPI Command Byte
The first byte clocked into the SPI interface is a command byte that sets: the register address; the
direction; and when operating as a USB peripheral device, a bit that directly sets the ACKSTAT
bit. In all SPI transactions, whether in or out, the bit ordering is b7 first, b0 last.
MOSI Bit Signal
7 REG4
6 REG3
5 REG2
4 REG1
3 REG0
2 0
1 Direction (1= Wr, 0 = Rd)
0 ACKSTAT (peripheral)
Figure 5. The SPI command byte.
An SPI cycle starts with the SPI master driving CS# low, then driving eight SPI clocks whose
rising edges strobe in the command byte. REG[4:0] set the register address, and the direction bit
sets the read or write direction for the SPI cycle. For USB peripheral operation, the ACKSTAT
bit writes the corresponding bit in the EPSTALLS register.
Following the command byte, the SPI master issues one or more groups of 8-SCK clocks to
clock byte data into or out of the MAX3421E. When accessing a FIFO, as long as CS# remains
low, the register address clocked in with the command remains in effect. This ability to burst
bytes is convenient when reading or writing the endpoint FIFOS. For example, to load 37 bytes
into the EP0FIFO (peripheral mode), the SPI master writes the command byte 00000010 which
selects R0 (EP0FIFO) for a write operation (direction bit is 1). Then it writes 37 bytes to the SPI
port, and finally drives CS# high to complete the SPI cycle.
Note: Both MOSI and MISO data are sampled on the rising edge of SCK. Data changes on the
falling edge of SCK.
The SPI cycle terminates when the SPI master return CS# to its high state.
SPI Modes
The SPI standard defines four clocking modes, reflecting two mode signals called CPOL (clock
polarity) and CPHA (clock phase). These signals are represented in the form (CPOL, CPHA). An
interface that expects both positive edge SCKS and the MOSI data to be available before the first
positive clock edge, can operate in modes (0,0) and (1,1) without alteration. This property allows
the MAX3421E to operate in mode (0,0) or (1,1) without requiring a mode pin.
The scope traces below illustrate identical data transfers between a microprocessor and the
MAX3421E.
Figure 6 uses SPI mode (0,0) and Figure 7 uses SPI mode (1,1). The difference is