Maxim MAX3421E, Руководство по программированию, Страница: 32 / 63

32
MAX3421E Programming Guide
GPIN(0-7), GPINPOL(0-7)
GPINIRQ(0-7), GPINIE (0-7)
Meaning:
GPIN General-Purpose Input pins 0 through 7
GPINPOL General-Purpose IN Interrupt Polarity 0 though 7
GPINIRQ General-Purpose IN Interrupt Request 0 through 7
GPINIE General-Purpose IN Interrupt Enable 0 through 7
Mode: Peripheral
and Host
GPIN
The CPU reads the GPIN pin states by reading the GPIN register bits. Only the outside circuitry
can control these register bit states. All eight GPIN pins are pulled up to V
CC
with weak (~20
k Ω ) internal resistors.
GPINPOL
The CPU sets the GPINPOL bits to set the edge polarity of the interrupt requests for each of the
GPIN pins (
Table 5 ). These bits are cleared at power-on. They retain their states either when
CHIPRES = 1 or after a mode change.
Table 5. Edge Polarity for the GPIN Interrupts
GPINPOL Polarity
0 neg edge
1 pos edge
GPINIRQ
The MAX3421E sets a GPIN Interrupt Request bit when a signal on the GPIN pin makes a
positive or negative transition. The GPINPOL bit (
Table 5
) controls the active edge polarity.
The GPINIRQ bits are active whether or not the individual GPIN interrupt enables or the IE bit
is set.
GPINIE
The CPU sets a GPIN Interrupt Enable bit to pass the corresponding IRQ bit through to the
interrupt logic feeding the MAX3421E INT pin. If IE = 1, an enabled IRQ appears either on the
INT pin if SEPIRQ = 0, or on the GPX pin if SEPIRQ = 1 and GPX[B:A] = 10.
Note: During normal operation, the GPIN interrupts are OR’d with all the other MAX3421E
interrupt sources indicated on the INT pin. It is also possible to detach the eight GPIN interrupt
request bits as INT pin sources and make them separately available as a group on the GPX pin.
In this mode, the GPX pin serves as a second MAX3421E INT output pin. This mode may be
preferred in systems that need to minimize detection time for external events. The
SEPIRQ bit
enables this separation of interrupt sources.