78M6612 Hardware Design Guidelines
AN_6612_007
12
Rev 2
V3P3
V3P3 -
400mV
V3P3 - 10mV
VBIAS
0V
Battery or
reset
mode
Normal
operation,
WDT
enabled
WDT dis-
abled
V1
5.3 V1 Pin
The V1 pin is connected to an internal power-fail comparator. The V1 input voltage is compared to an
internal reference voltage of 1.6 V (VBIAS). If the V1 voltage is above VBIAS, the comparator output is
high (1) signaling normal operation. If the V1 voltage is below VBIAS, the comparator output is low (0)
signaling battery mode operation (via an external battery attached to the VBAT pin). Connect the voltage
divider shown in Figure 9 to the V1 pin to enable normal (WDT enabled) 78M6612 operation. The
watchdog may be disabled for debugging by raising the V1 pin above 2.9 V.
R3 is used to provide hysteresis to the comparator.
The input pin V1 sinks 1 µA when V1< VBIAS and 0 µ
A when V1 ≥ VBIAS.
Therefore the thresholds are:
(High to Low transition, VBIAS = 1.6 VDC)
(Low to High transition, VBIAS = 1.6 VDC)
C1 provides additional filtering to the V1 input to prevent spurious commutations of the V1 comparator.
Figure 10: Voltage Divider
