29
5. MPEG Block Diagram
IC501
P
ANTERA
- Plus
IC301
XC9572VL
CPLD
I/O POR
T
72
IC304
SDRAM
16/32BIT
64M
IC305
93C56
EEPROM
IC306
FLASH
MEMOR
Y
IC302/IC303
LA
TCH
AD[0:7]
8
DSP
I/F
DVD[0:7]
8
LA[0:3]
4
SCLK,SDA
T
A
SQCK,SQS0
REQP
SDCLK1,PSYNC
DSP_INT
SENSE
/DSP_CS
AD[00:19]
RF &
MOT
OR
I/F
MIRR
LDON
SCLK, SDATA
EE_CS
F_IN
32
MD[00:31]
MCLK2
CKE
MA[00:10]
MA12,13
/CS0
/RAS/
/CAS
/WE
/DQM[0:3]
SPINDLE_FG
ALE
AD[04:19]
16
LADD[04:19]
16
LA[0:3]
4
AD[00:15]
16
AUDIO
I/F
DA
_DA
T
A
DA_BCK,DA_LRCK,DA_XCK
DAC_L0,DAC_L1
DAC_RST
A/V
JACK
I/F
C/R(B)
CVBS/G(R)
Y/B(G)
CVBS
V_MUTE,16:9
ZISENB
/RD
/PWED
II
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