9
10
7. BLOCK DIAGRAM
Q102 SAA7372GP
Q103
Q104
Q304 TDA1315
8. FLAG No.
No. Flag Name
Function
0
MT-OUT Motor Drive Output
1
HF-OUT TDA1302T HF signal output
2
3
HF-HPF
HF Signal HPF Output
4
LDON
Laser Diode Control Signal
5
6
RA
Radial Motor Control Signal(PDM)
7
FO
Focus Motor Control Signal(PDM)
8
SL
Slegde Motor Control Signal(PDM)
9
10
DIGO
Digital Audio Output Signal
11
CDR7
CD7(SAA7372) Reset Pulse
12
SILD
CD7(SAA7372) Servo Parte enable Signal
13
RAB7
CD7(SAA7372) Decorde and DSP parte enable signal
14
SCDC
CD7(SAA7372) data clock out signal
15
WCDC
CD7(SAA7372) data word clock out signal
16
SIIO
Servo pcb and Main pcb comunicateing signal
17
18
LRCK
SM5844AF(Q309) word clock signal
19
20
21
DADC
CD7(SAA7372) data out(16bit) signal
22
36MHz
Sampling frequency 48KHz/32KHz Master clock
23
33MHz
Sampling frequency 44KHz Master clock
24
SDA
From CPU(QF01) TO TDA1315H(Q304) data signal
25
SCL
From CPU(QF01) TO TDA1315H(Q304) clock signal
26
27
REST
CPU(QF01) Power on reset
28
RCDK
Main pcb SIIO Latch pulse for(Q501,Q502,Q503)
29
RCDG
SERVO PCB SIIO Latch pulse for QF06
30
31
32
33
34
35
OSC
CPU(QF01) self clock
36
OSC
CPU(QF01) self clock
37
38
39
40
41
LOCK
TDA1315H(Q304) unlock delayed output signal
42
EMPA
TDA1315H(Q304) Deemphasis output signal
43
DACD
CD7(SAA7372) data out signal
44
45
46
47
48
DMUT
from CPU(QF01) to TDA1315H(Q304) muting signal
49
50
FS32
TDA1315H(Q304) 32k Sampling detected signal
51
FS44
TDA1315H(Q304) 44.1k Sampling detected signal
52
FS48
TDA1315H(Q304) 48k Sampling detected signal
53
SD
TDA1315H(Q304) data output signal
54
WS
TDA1315H(Q304) Word select output signal
55
SCK
TDA1315H(Q304) data clock output signal
56
FRQ2
CD7(SAA7372) Operating clock out signal
57
UNLOCK TDA1315H(Q304) unlock output signal
58
59
COAX2
Digtal I/O input COAX2 signal
60
OPT0
Digtal I/O input OPTICAL signal
61
62
63
64
65
66
OUT+
Correct phase AUDIO SIGNAL
67
OUT-
Inverse phase AUDIO SIGNAL
68
69
REMU
Relay mute by POWER ON/OFF and selecting FILTER mode
70
71
72
73
74
75
76
77
78
79
768FS
Master clock selecting output
80
256FS
Master clock divided output
81
128FS
Master clock divided output
82
4FS
176.4KHz before Word select signal
83
WSDA
Word select for DSP(Q509) and DAC(QD03,QD53) 176.4KHz
84
FMUT
Filter select switching on time unenable for DAC
85
CLDA
DSP(Q509) data clock signal
86
BCEN
DSP(Q509) data clock enable signal for DAC
87
BCDA
for DAC(QD03,QD53) data clock 5.6448MHz
88
89
90
91
92
93
94
95
96
97
98
99
Содержание 74 CD7
Страница 8: ...7 8 6 WIRING DIAGRAM ...
Страница 10: ...9 SCHEMATIC DIAGRAM AND PARTS LOCATION 11 12 ...
Страница 11: ...13 14 ...
Страница 12: ...15 16 ...
Страница 13: ...17 18 ...
Страница 14: ...19 20 ...