LSI LSI53C896, Техническое руководство

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SCSI Registers 4-57
When it is set, MMWS contains bits [63:32] and
SCRATCH B contains bits [31:0] of the RAM Base
Address value from the PCI Configuration
Base Address
Register Two (SCRIPTS RAM) .
This is the base address for the internal 8 Kbytes internal
RAM.
Memory Move Read Selector (MMRS) contains
bits [63:32] and Scratch Register A (SCRATCHA)
contains bits [31:0] of the memory mapped operating
register base address. Bits [23:16] of
SCRIPTS Fetch
Selector (SFS) contain the PCI Revision ID (Rev ID)
register value and bits [15:0] contain the PCI Device ID
register value. When this bit is set, only reads to the
registers are affected, writes will pass through normally.
When this bit is cleared, the SCRATCH A, MMRS,
SCRATCH B, MMWS, and SFS registers return to normal
operation.
Note: Bit 3 is the only writable bit in this register. All other bits are
read only. When modifying this register, all other bits must
be written to zero. Do not execute a Read-Modify-Write to
this register.
TEOP SCSI True End of Process 2
This bit indicates the status of the LSI53C896 SCSI
function’s internal TEOP signal. The TEOP signal
acknowledges the completion of a transfer through the
SCSI portion of the LSI53C896 SCSI function. When this
bit is set, TEOP is active. When this bit is cleared, TEOP
is inactive.
DREQ Data Request Status 1
This bit indicates the status of the LSI53C896 SCSI
function’s internal Data Request signal (DREQ). When
this bit is set, DREQ is active. When this bit is cleared,
DREQ is inactive.
DACK Data Acknowledge Status 0
This bit indicates the status of the LSI53C896 SCSI
function’s internal Data Acknowledge signal (DACK/).
When this bit is set, DACK/ is inactive. When this bit is
cleared, DACK/ is active.
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