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PCI Configuration Space Register Description

4-5

Version 2.1

Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

function to respond to I/O Space accesses at the address
range the PCI Configuration Space

I/O Base Address

register specifies. Clearing this bit disables the PCI func-
tion’s response to I/O Space accesses.

Register: 0x06–0x07

Status
Read/Write

Reads to this register behave normally. To clear a bit location that is
currently set, write the bit to one (1). For example, to clear bit 15 when
it is set, without affecting any other bits, write 0x8000 to the register.

Detected Parity Error (from Slave)

15

This bit is set per the PCI Local Bus Specification, Revi-
sion 2.2, and PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0a.

Signalled System Error

14

The LSI53C1030 PCI function sets this bit when assert-
ing the SERR/ signal.

Received Master Abort (from Master)

13

A master device sets this bit when a Master Abort com-
mand terminates its transaction (except for Special
Cycle).

Received Target Abort (from Master)

12

A master device sets this bit when a Target Abort com-
mand terminates its transaction.

Reserved

11

This bit is reserved.

DEVSEL/ Timing

[10:9]

These two read only bits encode the timing of DEVSEL/
and indicate the slowest time that a device asserts
DEVSEL/ for any bus command except Configuration
Read and Configuration Write. The LSI53C1030 only

15

14

13

12

11

10

9

8

7

6

5

4

3

0

Status

0

0

0

0

0

0

1

0

0

0

1

1

0

0

0

0

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Содержание LSI53C1030

Страница 1: ...DB14 000156 04 LSI53C1030 PCI X to Dual Channel Ultra320 SCSI Multifunction Controller TECHNICAL MANUAL J u n e 2 0 0 3 Version 2 1...

Страница 2: ...uct described herein except as expressly agreed to in writing by LSI Logic nor does the purchase or use of a product from LSI Logic convey a license under any patent rights copyrights trademark rights...

Страница 3: ...The people who benefit from this book are Engineers and managers who are evaluating the LSI53C1030 for use in a system Engineers who are designing the LSI53C1030 into a system Organization This docume...

Страница 4: ...orld Wide Web Home Page www lsilogic com ANSI 11 West 42nd Street New York NY 10036 212 642 4900 Global Engineering Documents 15 Inverness Way East Englewood CO 80112 800 854 7179 or 303 397 7956 outs...

Страница 5: ...ID value Updated the ZCR behavior description Updated the Multi ICE test interface description Version 2 0 4 2002 Added register summary appendix Updated the electrical characteristics Updated the Ind...

Страница 6: ...vi Preface Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved...

Страница 7: ...Technology 1 8 1 7 Benefits of TolerANT Technology 1 8 1 8 Summary of LSI53C1030 Features 1 9 1 8 1 SCSI Performance 1 9 1 8 2 PCI Performance 1 10 1 8 3 Integration 1 11 1 8 4 Flexibility 1 11 1 8 5...

Страница 8: ...CI System Signals 3 4 3 2 2 PCI Address and Data Signals 3 5 3 2 3 PCI Interface Control Signals 3 6 3 2 4 PCI Arbitration Signals 3 7 3 2 5 PCI Error Reporting Signals 3 7 3 2 6 PCI Interrupt Signals...

Страница 9: ...r 5 Specifications 5 1 DC Characteristics 5 1 5 2 TolerANT Technology Electrical Characteristics 5 7 5 3 AC Characteristics 5 9 5 4 External Memory Timing Diagrams 5 11 5 4 1 NVSRAM Timing 5 12 5 4 2...

Страница 10: ...x Contents Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved...

Страница 11: ...3C1030 Functional Signal Grouping 3 3 5 1 LVD Driver 5 3 5 2 LVD Receiver 5 4 5 3 Rise and Fall Time Test Condition 5 8 5 4 SCSI Input Filtering 5 9 5 5 External Clock 5 10 5 6 Reset Input 5 10 5 7 In...

Страница 12: ...xii Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved...

Страница 13: ...ntrol Signals 3 12 3 11 SCSI Channel 1 Interface Signals 3 13 3 12 SCSI Channel 1 Control Signals 3 14 3 13 Flash ROM NVSRAM Interface Pins 3 14 3 14 Serial EEPROM Interface Pins 3 16 3 15 ZCR Configu...

Страница 14: ...PAR64 PERR REQ64 SERR STOP TRDY 5 5 5 9 Input Signals CLK CLKMODE_0 CLKMODE_1 DIS_PCI_FSN DIS_SCSI_FSN GNT IDDTN IDSEL IOPD_GNT PVT1 PVT2 SCANEN SCANMODE SCLK TCK_CHIP TCK_ICE TESTACLK TESTCLKEN TEST...

Страница 15: ...xv Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved A 2 LSI53C1030 PCI I O Space Registers A 3 A 3 LSI53C1030 PCI I O Space Registers A 4...

Страница 16: ...xvi Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved...

Страница 17: ...ion 1 6 Benefits of LVDlink Technology Section 1 7 Benefits of TolerANT Technology Section 1 8 Summary of LSI53C1030 Features 1 1 General Description The LSI53C1030 PCI X to Dual Channel Ultra320 SCSI...

Страница 18: ...ation units QAS minimizes SCSI bus latency by allowing the bus to directly enter the arbitration selection bus phase after a SCSI disconnect and skip the bus free phase Skew compensation permits the L...

Страница 19: ...een the host system and SCSI devices with minimal host processor intervention Fusion MPT technology provides an efficient architecture that solves the protocol overhead problems of previous intelligen...

Страница 20: ...ting system The IM firmware requires a configuration mechanism which enables configuration of the mirroring attributes during initial setup or reconfiguration after hardware failures or changes in the...

Страница 21: ...0 Developed from the proven LSI Logic SDMS solution the Fusion MPT architecture delivers unmatched performance of up to 100 000 Ultra320 SCSI I Os per second with minimal system overhead or device mai...

Страница 22: ...ersions of the PCI PCI X specification The LSI53C1030 is a true multifunction PCI X device and presents a single electrical load to the PCI bus The LSI53C1030 uses a single REQ GNT pair to arbitrate f...

Страница 23: ...r levels of data reliability by ensuring complete integrity of transferred data CRC is a 32 bit scheme referred to as CRC 32 CRC guarantees detection of all single or double bit errors as well as any...

Страница 24: ...lled up by terminators TolerANT receiver technology improves data integrity in unreliable cabling environments where other devices would be subject to data corruption TolerANT receivers filter the SCS...

Страница 25: ...Mandatory packetized protocol Quick arbitrate and select QAS Skew compensation with bus training Transmitter precompensation to overcome ISI effects for SCSI data signals Retained training information...

Страница 26: ...on 1 1 Complies with PC2001 System Design Guide Offers unmatched performance through the Fusion MPT architecture Provides high throughput and low CPU utilization to off load the host processor Present...

Страница 27: ...Reduces time to market with the Fusion MPT architecture Single driver binary for SCSI and Fibre Channel products Thin easy to develop drivers Reduced integration and certification effort Provides int...

Страница 28: ...ds and internal chip logic Supports CRC checking and generation in Double Transition DT phases Provides comprehensive SureLINK Domain Validation technology Basic Level 1 with inquiry command Enhanced...

Страница 29: ...l Memory Interface Section 2 6 Serial EEPROM Interface Section 2 7 Zero Channel RAID Section 2 8 Multi ICE Test Interface The LSI53C1030 is a high performance intelligent PCI X to Dual Channel Ultra32...

Страница 30: ...ing components Host Interface Module Up to a 64 bit 133 MHz PCI PCI X Interface System Interface I O Processor IOP DMA Arbiter and Router Shared RAM External Memory Interface Flash ROM Memory Controll...

Страница 31: ...supports the external memory serial EEPROM and General Purpose I O GPIO interfaces This section provides a detailed explanation of the host interface submodules U320 SCSI Datapath Engine Secondary 0 B...

Страница 32: ...us with the system interface registers PCI Memory Space 0 and the PCI I O Base Address registers identify the location of the system interface register set Chapter 4 PCI Host Register Description prov...

Страница 33: ...ses the NVSRAM for IM technology For a detailed description of this block refer to Section 2 5 External Memory Interface During power up or reset the LSI53C1030 uses the MAD 15 0 and MADP 1 0 signals...

Страница 34: ...path Engines The datapath engines manage the SCSI side of DMA transactions between their individual SCSI bus and the host system 2 1 2 3 Context Managers The context managers are ARM966E S processors...

Страница 35: ...payload The header uniquely identifies the message The payload contains information that is specific to the request Reply message frame descriptors have one of two formats and are passed through the r...

Страница 36: ...PCI Configuration Space registers for each PCI function Each configuration space is a contiguous 256 x 8 bit set of addresses The system BIOS initializes the configuration registers using PCI configur...

Страница 37: ...ic memory accesses The LSI53C1030 requires 64 Kbytes of memory space The PCI specification defines memory space as a contiguous 64 bit memory address that all system resources share The Memory 0 Low a...

Страница 38: ...te Block PCI N A PCI X No PCI N A PCI X Yes 0b1010 Configuration Read Configuration Read No Yes 0b1011 Configuration Write Configuration Write No Yes 0b1100 Memory Read Multiple Split Completion Yes Y...

Страница 39: ...res the upper 32 address bits The LSI53C1030 supports this command when operating in either the PCI or PCI X bus mode 2 3 2 5 Memory Read Command The LSI53C1030 uses the Memory Read command to read da...

Страница 40: ...PCI bus selects the LSI53C1030 by asserting its IDSEL signal when AD 1 0 equal 0b00 During the address phase of a configuration cycle AD 7 2 address one of the 64 Dword registers in the configuration...

Страница 41: ...line size based on the amount of data to transfer 2 3 2 13 Split Completion Command Split transactions in PCI X replace the delayed transactions in conventional PCI The LSI53C1030 supports up to eight...

Страница 42: ...Size register The LSI53C1030 determines when to issue a Write and Invalidate command instead of a Memory Write command and supports this command when operating in the PCI bus mode Alignment The LSI53...

Страница 43: ...che Mode The LSI53C1030 supports an 8 bit Cache Line Size register The Cache Line Size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries T...

Страница 44: ...further categorized as D3hot or D3cold Powering a function off places it in the D3cold Power State Bits 1 0 of the Power Management Control Status register independently control the power state of eac...

Страница 45: ...aces the SCSI core in the coma mode Placing the PCI Function in Power State D2 disables the SCSI and DMA interrupts and suppresses the following PCI Configuration Space Command register enable bits I...

Страница 46: ...LSI53C1030 controller supports the Ultra320 SCSI Ultra160 SCSI Ultra2 SCSI Ultra SCSI and Fast SCSI interfaces 2 4 1 Ultra320 SCSI Features This section describes how the LSI53C1030 implements the fe...

Страница 47: ...transmitting device indicates the start of valid data state by holding the state of the P1 line for the first two data transfer periods Beginning on the third data transfer period the transmitting de...

Страница 48: ...ecompensation to adjust the strength of the REQ ACK parity and data signals When a signal transitions to HIGH or LOW the LSI53C1030 boosts the signal drive strength for the first data transfer period...

Страница 49: ...s transfer agreement or a paced transfer agreement before performing packetized transfers The number of bytes in an information unit transfer is always a multiple of four If the number of bytes to tra...

Страница 50: ...ion the LSI53C1030 can either execute this training pattern during each connection or can execute the training pattern store the adjustment parameters and recall them on subsequent connections with th...

Страница 51: ...ctivity and SCSI cable length the LSI53C1030 features LVDlink technology which is the LSI Logic implementation of LVD SCSI LVDlink transceivers provide the inherent reliability of differential SCSI an...

Страница 52: ...p to 1 Mbyte of address space The interface supports byte word and Dword accesses The LSI53C1030 Dword aligns Dword reads word aligns word reads and byte aligns byte reads The remaining bits from word...

Страница 53: ...the Flash is a 16 byte burst read beginning at Flash address 0x000000 The LSI53C1030 compares the values read to the Flash signature values that Table 2 4 provides If the signature values match the LS...

Страница 54: ...rent to the BIOS drivers and operating system Figure 2 5 provides a block diagram illustrating how to connect the NVSRAM This design employs the CPLD to latch the address instead of using separate add...

Страница 55: ...rom the serial EEPROM For more information on the setting of the power on options refer to Section 3 10 Power On Sense Pins Description A 2 wire serial interface provides the connection to the serial...

Страница 56: ...ignal has no effect on the LSI53C1030 operation Pulling ZCR_EN LOW enables ZCR operation When ZCR is enabled the LSI53C1030 responds to PCI configuration cycles when the IOPD_GNT and IDSEL signal are...

Страница 57: ...ng from LSI53C1010R based designs to LSI53C1030 based designs Notice that the LSI53C1030 does not require the 2 1 mux Figure 2 6 ZCR Circuit Diagram for LSI53C1030 and LSI53C1010R ZCR PCI Slot LSI53C1...

Страница 58: ...port This header is essential for debugging both the firmware and the design functionality and must be included in board designs The connector is a 20 pin header that mates with the IDC sockets mounte...

Страница 59: ...ganization Section 3 2 PCI Bus Interface Signals Section 3 3 PCI Related Signals Section 3 4 SCSI Interface Signals Section 3 5 Memory Interface Section 3 6 Zero Channel RAID Interface Section 3 7 Tes...

Страница 60: ...l Purpose I O GPIO Interface There are five signal types I Input a standard input only signal O Output a standard output driver typically a Totem Pole output I O Input and output bidirectional P Power...

Страница 61: ..._SRST B_SSEL B_SD 15 0 B_DIFFSENS A_DIFFSENS LSI53C1030 SCSI Function A SCSI Function B Test Interface SCSI Bus Interface System Address and Data Interface Control Arbitration Error Reporting Interrup...

Страница 62: ...al groups 3 2 1 PCI System Signals Table 3 1 describes the PCI System signals group Table 3 1 PCI System Signals Signal Name BGA Position Type Strength Description CLK AC22 I N A Refer to the PCI Loca...

Страница 63: ...22 AB19 AD21 AF24 AC20 AE23 AC21 I O 8 mA PCI Refer to the PCI Local Bus Specification Version 2 2 and the PCI X Addendum to the PCI Local Bus Specification Version 1 0a for this signal description C_...

Страница 64: ...o the PCI Local Bus Specification Version 1 0a for this signal description IRDY AE15 I O 8 mA PCI Refer to the PCI Local Bus Specification Version 2 2 and the PCI X Addendum to the PCI Local Bus Speci...

Страница 65: ...PCI Local Bus Specification Version 1 0a for this signal description GNT AE8 I N A Refer to the PCI Local Bus Specification Version 2 2 and the PCI X Addendum to the PCI Local Bus Specification Versi...

Страница 66: ...signal description The LSI53C1030 can route interrupts to INTA and or ALT_INTA The interrupt request routing mode bits bits 9 8 in the PCI Host Interrupt Mask register control the routing of interrup...

Страница 67: ...n drain signal The interrupt request routing mode bits bits 9 8 in the PCI Host Interrupt Mask register control the routing of interrupt signals to INTA and or ALT_INTA ALT_INTB AB9 O 8 mA PCI Active...

Страница 68: ...oes not support the HVD mode If HVD signalling is present the SCSI channel 3 states its drivers 3 4 1 SCSI Channel 0 Signals Table 3 9 describes the SCSI Channel 0 Interface signals Table 3 8 SCSI Bus...

Страница 69: ...ts the present mode of the SCSI bus This signal is 5 V tolerant and must connect to the DIFFSENS signal on the physical SCSI bus SE Mode Driving this pin below 0 5 V LOW indicates an SE bus and places...

Страница 70: ...ength Description A_SCD A_SCD A_SIO A_SIO A_SMSG A_SMSG A_SREQ A_SREQ A_SACK A_SACK A_SBSY A_SBSY A_SATN A_SATN A_SRST A_SRST A_SSEL A_SSEL K3 K4 K5 J5 L2 L1 J2 J3 M5 L5 N3 N4 M4 N5 M1 M2 L4 K2 I O SE...

Страница 71: ...ignals B_VDDBIAS B13 O N A B_VDDBIAS provides power for the B_RBIAS circuit B_RBIAS A11 I N A Connect a 9 76 k or 10 0 k resistor between the B_VVDBIAS and B_RBIAS pins to generate the LVD signalling...

Страница 72: ...SG B_SREQ B_SREQ B_SACK B_SACK B_SBSY B_SBSY B_SATN B_SATN B_SRST B_SRST B_SSEL B_SSEL E16 D17 E17 D18 B16 D16 B18 C18 D14 E14 A15 B15 B14 D13 E15 A16 B17 C17 I O SE 48 mA LVD 12 mA SCSI Channel 1 Com...

Страница 73: ...E G26 O 4 mA The LSI53C1030 asserts active LOW Memory Output Enable to indicate that the selected NVSRAM or Flash ROM device can drive data This signal is typically an asynchronous input to NVSRAM and...

Страница 74: ...esistor when an EEPROM is present SerialDATA H26 I O 8 mA Serial EEPROM data This signal requires a 4 7 k external pull up resistor when an EEPROM is present Table 3 15 ZCR Configuration Pins Signal N...

Страница 75: ...ovides the JTAG test mode select signal RTCK_ICE AA5 O 8 mA Test Clock Acknowledge provides the JTAG test clock acknowledge signal for the In Circuit Emulator ICE debug logic TRST_ICE AB4 I N A Test R...

Страница 76: ...E_0 is for use only by LSI Logic CLKMODE_1 AC2 I N A CLKMODE_1 is for use only by LSI Logic DIS_PCI_FSN A24 I N A Pulling DIS_PCI_FSN LOW disables the PCI FSN Pulling this pin HIGH allows the chip to...

Страница 77: ...s these signals and can configure them as inputs or as outputs These pins default to input mode after chip initialization A_LED J23 O 12 mA A_LED either drives the SCSI Channel 0 activity LED or provi...

Страница 78: ...U1 V26 W3 Y24 AA1 AB26 AC3 AD7 AD11 AD15 AD19 AD23 AE1 AF2 AF6 AF10 AF14 AF18 AF22 AF26 G N A VSS_IO provides ground for the PCI bus drivers receivers SCSI bus drivers receivers local memory interfac...

Страница 79: ...urations to employ the default settings Provide pull up options for all MAD pins Table 3 20 MAD Power On Sense Pin Options MAD Pin Function Pulled Down Default Pulled Up MADP 1 Reserved MADP 0 PCI X M...

Страница 80: ...egister MAD 14 64 bit PCI By default internal logic pulls this pin LOW to enable 64 bit PCI operation and to set the 64 bit Enable bit in the PCI X Status register Pulling this pin HIGH configures the...

Страница 81: ...11 10 are pulled HIGH MAD 6 IOP Boot Enable By default internal logic pulls this pin LOW In the default mode the IOP starts the boot process and downloads firmware from the Flash ROM Pulling this pin...

Страница 82: ...the pin encoding By default internal logic pulls these pins LOW to indicate that a Flash ROM is not present in the system MAD 0 Reserved Table 3 21 PCI X Function to SCSI Channel Configurations MAD 5...

Страница 83: ...wn SerialDATA SerialCLK H26 J25 Internal Pull down Pull up externally when connected to a serial EEPROM GPIO 7 0 K25 L23 L25 M25 H25 K24 AE25 AC23 Internal Pull down TST_RST AD5 Internal Pull up TCK_C...

Страница 84: ...3 26 Signal Description Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved...

Страница 85: ...pin and its own PCI Address space The PCI System Address space consists of three regions Configuration Space Memory Space and I O Space PCI Configuration Space supports the identification configurati...

Страница 86: ...e Device ID Vendor ID 0x00 4 3 Status Command 0x04 4 3 Class Code Revision ID 0x08 4 7 Reserved Header Type Latency Timer Cache Line Size 0x0C 4 7 I O Base Address 0x10 4 9 Memory 0 Low 0x14 4 10 Memo...

Страница 87: ...particular device The default Device ID for the LSI53C1030 is 0x0030 Register 0x04 0x05 Command Read Write The Command register provides coarse control over the PCI function s ability to generate and...

Страница 88: ...is bit is reserved Write and Invalidate Enable 4 Setting this bit enables the PCI function to generate write and invalidate commands on the PCI bus when operating in the conventional PCI mode Reserved...

Страница 89: ...bit is set per the PCI Local Bus Specification Revi sion 2 2 and PCI X Addendum to the PCI Local Bus Specification Revision 1 0a Signalled System Error 14 The LSI53C1030 PCI function sets this bit whe...

Страница 90: ...ower On Sense pin controls this bit Allowing the internal pull down to pull MAD 13 LOW sets this bit and indicates to the host system that the LSI53C1030 PCI function is capable of operating at 66 MHz...

Страница 91: ...lass code the middle byte is a subclass code and the lower byte identifies a specific register level programming inter face The value of this register is 0x010000 which iden tifies a SCSI controller R...

Страница 92: ...the value of the Latency Timer for this PCI bus master If the LSI53C1030 initializes in the PCI mode the default value of this register is 0x00 If the LSI53C1030 initializes in the PCI X mode the defa...

Страница 93: ...I O Base Address register maps the operating register set into I O Space The LSI53C1030 requires 256 bytes of I O Space for this base address register Hardware sets bit 0 to 0b1 Bit 1 is reserved and...

Страница 94: ...at the memory data is not prefetchable The LSI53C1030 requires 1024 bytes of memory space Memory 0 Low 31 0 This field contains the Memory 0 Low address Register 0x18 0x1B Memory 0 High Read Write The...

Страница 95: ...the memory data is not prefetchable The LSI53C1030 requires 64 Kbytes of memory for Memory Space 1 Memory 1 Low 31 0 This field contains the Memory 1 Low address Register 0x20 0x23 Memory 1 High Read...

Страница 96: ...register provides a mechanism for an add in card vendor to distinguish their cards from another vendor s cards even if the cards use the same PCI controller and have the same Vendor ID and Device ID T...

Страница 97: ...e PCI controller and have the same Vendor ID and Device ID The board designer can store a ven dor specific 16 bit value in an external serial EEPROM The ID Control Power On Sense pins MAD 11 for PCI F...

Страница 98: ...Address 31 11 These bits correspond to the upper 21 bits of the expan sion ROM base address The host system detects the size of the external memory by first writing 0xFFFFFFFF to this register and the...

Страница 99: ...ng Depending on the system configuration the device can optionally use an expansion ROM Note that to access the expansion ROM the user must also set bit 1 in the PCI Command register Register 0x34 Cap...

Страница 100: ...he system This register indicates the system interrupt con troller input to which this PCI function s interrupt pin con nects System architecture determines the values in this register Register 0x3D I...

Страница 101: ...Grant Read Only Min_Gnt 7 0 This register specifies the desired settings for the latency timer values in units of 0 25 s This register specifies how long of a burst period the device needs The LSI53C...

Страница 102: ...This register contains the pointer to the next item in the PCI function s extended capabilities list The value of this register varies according to system configuration Register 0xXX Power Management...

Страница 103: ...on is required before a generic class device driver can use it Reserved 4 This bit is reserved PME Clock 3 The LSI53C1030 clears this bit since the chip does not provide a PME pin Version 2 0 The PCI...

Страница 104: ...oes not provide a PME signal and disables PME asser tion Reserved 7 2 This field is reserved Power State 1 0 These bits determine the current power state of the LSI53C1030 Power states are Register 0x...

Страница 105: ...s register Register 0xXX MSI Capability ID Read Only MSI Capability ID 7 0 This register indicates the type of the current data struc ture This register always returns 0x05 indicating Mes sage Signall...

Страница 106: ...tem software allocates all or a subset of the requested messages by writing to this field The number of allocated request messages must align to a power of two Table 4 3 provides the bit encoding of...

Страница 107: ...etting this bit to mask interrupts on the INTx or ALT_INTx pins is a violation of the PCI specification Register 0xXX Message Address Read Write Message Address 31 2 This register contains message add...

Страница 108: ...it The LSI53C1030 sends an interrupt message by writing a Dword to the address held in the Message Address and Message Upper Address registers This register forms bits 15 0 of the Dword message that t...

Страница 109: ...ctions 6 4 These bits indicate the maximum number of split transac tions the LSI53C1030 can have outstanding at one time The LSI53C1030 uses the most recent value of this reg ister each time it prepar...

Страница 110: ...e 0 The host device driver sets this bit to allow the LSI53C1030 to attempt to recover from data parity errors If the user clears this bit and the LSI53C1030 is operating in the PCI X mode the LSI53C1...

Страница 111: ...es Designed Maximum Outstanding Split Transactions 25 23 These read only bits indicate a number greater than or equal to the maximum number of all outstanding split transactions for the LSI53C1030 PCI...

Страница 112: ...PCI bus Pulling MAD 15 HIGH clears this bit and disables 133 MHz operation of the PCI bus Refer to Section 3 10 Power On Sense Pins Description for more information concerning the Power On Sense pins...

Страница 113: ...Memory Space 0 and PCI Memory Space 1 form the PCI Memory Space PCI Memory 0 supports normal memory accesses while PCI Memory Space 1 supports diagnostic memory accesses For all registers except the D...

Страница 114: ...4 Diagnostic Read Write Address 0x0014 4 35 Reserved 0x0018 0x002F Host Interrupt Status 0x0030 4 36 Host Interrupt Mask 0x0034 4 37 Reserved 0x0038 0x003F Request FIFO 0x0040 4 38 Reply FIFO 0x0044 4...

Страница 115: ...e IOP processor writes to the System Interface Registers Doorbell register the LSI53C1030 generates a maskable interrupt to the PCI system The host system can read the value written by the IOP in the...

Страница 116: ...Diagnostic reg isters perform a write of any value except the Write I O Key sequence to the Write Sequence register The Diag nostic Write Enable bit bit 7 in the Host Diagnostic reg ister indicates t...

Страница 117: ...this bit to help coordinate recovery between multiple driver instances in a multifunction PCI implemen tation Diagnostic Read Write Enable 4 Setting this bit enables access to the Diagnostic Read Writ...

Страница 118: ...Read Write Data Read Write This register reads or writes Dword locations on the LSI53C1030 internal bus This register is only accessible through PCI I O Space and returns 0xFFFFFFFF if read through PC...

Страница 119: ...ough PCI I O Space and returns 0xFFFFFFFF if read through PCI Memory Space The host can enable write access to this register by writing the correct Write I O Key to the Write Sequence register and set...

Страница 120: ...oorbell message by clearing the corresponding system request interrupt Reserved 30 4 This field is reserved Reply Interrupt 3 The LSI53C1030 sets this bit when the Reply Post FIFO is not empty The LSI...

Страница 121: ...PCI interrupts to the INTx or ALT_INTx pins according to the bit encodings in Table 4 9 If the host system enables MSI the LSI53C1030 does not sig nal PCI interrupts on the INTx or ALT_INTx pins Rese...

Страница 122: ...nctions The two PCI functions physically share this register Request FIFO 31 0 For reads the Request Free MFA is empty and this reg ister contains 0xFFFFFFFF For writes the register con tains the Requ...

Страница 123: ...Section 5 3 AC Characteristics Section 5 4 External Memory Timing Diagrams Section 5 5 Package Drawings Please refer to the PCI Local Bus Specification the PCI X Addendum to the PCI Local Bus Specific...

Страница 124: ...ly voltage 0 3 3 9 V VIN Input voltage 0 5 VDD 0 5 V ILP 2 Latch up current 150 mA 2 V VPIN 8 V T2 Lead temperature 125 C ESD2 2 SCSI pins only Electrostatic discharge 2000 V MIL STD 883C Method 3015...

Страница 125: ...ource current 6 5 13 5 mA Asserted state IO Sink current 6 5 13 5 mA Asserted state IO Source current 2 5 9 5 mA Negated state IO Sink current 2 5 9 5 mA Negated state IOZ 3 state leakage 20 A RL 2 VC...

Страница 126: ...e 0 7 1 9 V Note 1 VIL SE sense voltage VSS 0 35 0 5 V Note 1 IOZ 3 state leakage 10 10 A VPIN 0 V 3 6 V 1 VIH VIL and Vs are specified in the SPI 4 draft specification Table 5 6 Input Capacitance Sym...

Страница 127: ...IRDY PAR PAR64 PERR REQ64 SERR STOP TRDY Symbol Parameters Min Max Unit Test Conditions VIH Input high voltage 0 5 VDD PCI5VBIAS1 V VIL Input low voltage 0 5 0 3 VDD V VOH Output high voltage 0 9 VDD...

Страница 128: ...rmation given does not apply to these signals Table 5 10 8 mA Output Signals1 ADSC ADV ALT_INTA ALT_INTB BWE 1 0 FLSHALE 1 0 FLSHCE INTA INTB MCLK MOE PIPESTAT 2 0 RAMCE REQ RTCK_ICE SerialCLK SERR TD...

Страница 129: ...SCSI signals Table 5 12 TolerANT Technology Electrical Characteristics for SE SCSI Signals1 Symbol Parameter Min Max Units Test Conditions VOH 2 Output high voltage 2 5 3 7 V IOH 0 mA VOL Output low...

Страница 130: ...883C Method 3015 7 100 pF at 1 5 k ESDCDM Electrostatic discharge CDM 0 5 kV ESD DS5 3 1 1996 Latch up 100 mA Filter delay 20 30 ns Figure 5 4 Ultra filter delay 10 15 ns Figure 5 4 Ultra2 filter del...

Страница 131: ...rnal clock timing data REQ or ACK Input t1 VTH Note t1 is the input filtering period Table 5 13 External Clock Symbol Parameter 133 MHz PCI X 66 MHz PCI X 66 MHz PCI 33 MHz PCI Units Min Max Min Max M...

Страница 132: ...1 4 V t1 t3 t4 t2 Table 5 14 Reset Input Symbol Parameter Min Max Units t1 Reset pulse width 10 ns t2 Reset deasserted setup to CLK HIGH 0 ns t3 MAD setup time to CLK HIGH for configuring the MAD bus...

Страница 133: ...sion 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved Figure 5 7 Interrupt Output 5 4 External Memory Timing Diagrams This section provides timing diagrams and data for NVSRAM...

Страница 134: ...bus NVSRAM read accesses Table 5 16 NVSRAM Read Cycle Timing Symbol Parameter Min Max Unit t1 Address setup to FLSHALE HIGH 25 ns t2 Address hold from FLSHALE HIGH 25 ns t3 FLSHALE pulse width 25 ns t...

Страница 135: ...gh Order Address Middle Order Address FLSHALE1 Driven by LSI53C1030 FLSHALE0 Driven by LSI53C1030 RAMCE Driven by LSI53C1030 MOE Driven by LSI53C1030 BWE0 Driven by LSI53C1030 t3 t1 t2 t4 t5 t6 Low Or...

Страница 136: ...e Cycle Symbol Parameter Min Max Unit t11 Address setup to FLSHALE HIGH 25 ns t12 Address hold from FLSHALE HIGH 25 ns t13 FLSHALE pulse width 25 ns t20 Data setup to BWE0 LOW 40 ns t21 Data hold from...

Страница 137: ...e Order Address Low Order Address FLSHALE1 Driven by LSI53C1030 FLSHALE0 Driven by LSI53C1030 RAMCE Driven by LSI53C1030 MOE Driven by LSI53C1030 BWE0 Driven by LSI53C1030 t13 t11 t12 t24 t25 Write Da...

Страница 138: ...cesses Table 5 18 Flash ROM Read Cycle Timing Symbol Parameter Min Max Unit t1 Address setup to FLSHALE HIGH 25 ns t2 Address hold from FLSHALE HIGH 25 ns t3 FLSHALE pulse width 25 ns t4 Address valid...

Страница 139: ...High Order Address Middle Order Address FLSHALE1 Driven by LSI53C1030 FLSHALE0 Driven by LSI53C1030 FLSHCE Driven by LSI53C1030 MOE Driven by LSI53C1030 BWE0 Driven by LSI53C1030 t3 t1 t2 t4 t5 t6 Lo...

Страница 140: ...ite Cycle Symbol Parameter Min Max Unit t11 Address setup to FLSHALE HIGH 25 ns t12 Address hold from FLSHALE HIGH 25 ns t13 FLSHALE pulse width 25 ns t20 Data setup to BWE0 LOW 40 ns t21 Data hold fr...

Страница 141: ...ddle Order Address Low Order Address FLSHALE1 Driven by LSI53C1030 FLSHALE0 Driven by LSI53C1030 FLSHCE Driven by LSI53C1030 MOE Driven by LSI53C1030 BWE0 Driven by LSI53C1030 t13 t11 t12 t24 t25 Writ...

Страница 142: ...5 20 Specifications Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved 5 5 Package Drawings Figure 5 12 illustrates the signal locations on the Ball Grid Array BGA...

Страница 143: ...Package Drawings 5 21 Version 2 1 Copyright 2001 2002 2003 by LSI Logic Corporation All rights reserved This page left blank intentionally...

Страница 144: ...M3 M4 M5 M11 M12 M13 A_SRST A_SRST VDD_IO A_SATN A_SACK VSS_IO VSS_IO VSS_IO N1 N2 N3 N4 N5 N11 N12 N13 VSS_IO VDDC A_SBSY A_SBSY A_SATN VSS_IO VSS_IO VSS_IO P1 P2 P3 P4 P5 P11 P12 P13 VDD_IO VSSC A_S...

Страница 145: ...IO5 AD34 M14 M15 M16 M22 M23 M24 M25 M26 VSS_IO VSS_IO VSS_IO VDDC PCI5VBIAS VSS_IO GPIO4 AD35 N14 N15 N16 N22 N23 N24 N25 N26 VSS_IO VSS_IO VSS_IO SCANEN ZCR_EN AD32 AD33 VDD_IO P14 P15 P16 P22 P23 P...

Страница 146: ...D50 W26 AD51 V25 AD52 U24 AD53 V23 AD54 V24 AD55 U22 AD56 V22 AD57 Y26 AD58 Y25 AD59 W23 AD60 AA25 AD61 AC26 AD62 AB25 AD63 W22 A_DIFFSENS E2 ADSC D21 ADV B23 A_LED J23 ALT_INTA AF7 ALT_INTB AB9 A_RBI...

Страница 147: ...AB6 TESTHCLK AE2 TMS_CHIP AE4 TMS_ICE Y5 TN C5 TRACECLK B3 TRACEPKT0 D4 TRACEPKT1 B2 TRACEPKT2 F5 TRACEPKT3 E4 TRACEPKT4 C2 TRACEPKT5 E3 TRACEPKT6 G5 TRACEPKT7 F4 TRACESYNC E5 TRDY AE16 TRST_ICE AB4...

Страница 148: ...ADV B24 MADP0 B25 MAD13 B26 VSS_IO C1 VDDA C2 TRACEPKT4 C3 PIPESTAT2 C4 VSS_IO C5 TN C6 B_SD13 C7 VDD_IO C8 VSS_IO C9 B_SD2 C10 B_SD4 C11 VDD_IO C12 VSS_IO C13 B_SDP0 C14 VSSC C15 VDD_IO C16 VSS_IO C1...

Страница 149: ...24 AD52 U25 AD48 U26 VDD_IO V1 VDD_IO V2 A_SD2 V3 A_SD0 V4 A_SD1 V5 A_SD1 V22 AD56 V23 AD53 V24 AD54 V25 AD51 V26 VSS_IO W1 A_SDP1 W2 A_SDP1 W3 VSS_IO W4 A_SD0 W5 A_SD15 W22 AD63 W23 AD59 W24 VDD_IO W...

Страница 150: ...ts reserved Figure 5 13 456 Pin EPBGA KY Mechanical Drawing Important This drawing may not be the latest version For board layout and manufacturing obtain the most recent engineering drawings from you...

Страница 151: ...and 0x04 0x05 Read Write 4 3 Status 0x06 0x07 Read Write 4 5 Revision ID 0x08 Read Write 4 7 Class Code 0x09 0x0B Read Only 4 7 Cache Line Size 0x0C Read Write 4 7 Latency Timer 0x0D Read Write 4 8 He...

Страница 152: ...Read Only 4 18 Power Management Control Status Read Write 4 19 Power Management Bridge Support Extensions Read Only 4 20 Power Management Data Read Only 4 21 MSI Capability ID Read Only 4 21 MSI Next...

Страница 153: ...Sequence 0x04 Read Write 4 31 Host Diagnostic 0x08 Read Write 4 32 Test Base Address 0x0C Read Write 4 34 Diagnostic Read Write Data 0x10 Read Write 4 34 Diagnostic Read Write Address 0x14 Read Write...

Страница 154: ...ead Write Page System Doorbell 0x00 Read Write 4 31 Write Sequence 0x04 Read Write 4 31 Host Diagnostic 0x08 Read Write 4 32 Test Base Address 0x0C Read Write 4 34 Reserved 0x10 0x2F Reserved Host Int...

Страница 155: ...IAS 3 11 absolute maximum stress ratings 5 2 AC characteristics 5 9 ACK64 3 6 5 5 active LOW 3 1 active termination 2 23 AD 31 0 5 5 AD 63 0 3 5 5 5 address diagnostic read write 4 35 latches 3 15 add...

Страница 156: ...4 6 PME clock 4 19 PME enable 4 20 PME status 4 19 PME support 4 18 power management version 4 19 power state 4 20 received master abort from master 4 5 received split completion error message 4 27 r...

Страница 157: ...4 29 diagnostic memory enable bit 4 33 diagnostic read write address register 4 32 4 33 4 35 diagnostic read write data register 4 32 4 33 4 34 4 35 diagnostic read write enable bit 4 33 diagnostic wr...

Страница 158: ...ost interrupt mask register 2 16 3 8 3 9 4 36 4 37 host interrupt status register 4 36 4 37 host system 2 6 hot plug 5 7 HVD 2 23 3 10 3 11 3 13 sense voltage 5 4 hysteresis 5 7 I I O base address 4 5...

Страница 159: ...13 4 6 MAD 14 4 28 MAD 15 0 2 5 3 15 3 21 3 25 5 5 MAD 15 4 28 MAD 2 1 2 24 MAD 3 2 26 MAD 7 0 2 5 2 24 3 15 MAD 7 4 12 4 13 MADP 0 2 5 MADP 1 0 2 5 3 15 3 21 3 25 5 5 margin control settings 2 18 ma...

Страница 160: ...rallel protocol request 2 18 2 22 parity error 4 6 passive termination 2 23 PC2001 system design guide 1 10 2 16 PCI 1 11 2 6 33 MHz 5 9 64 bit 3 21 3 22 66 MHz 3 21 3 22 5 9 66 MHz capable bit 4 6 ad...

Страница 161: ...mpletion command 2 13 status 3 22 system address space 4 1 system signals 3 4 PCI_CAP 3 22 PCI_GNT 3 16 PCI5VBIAS 1 11 3 20 5 5 PCI SIG 4 12 PCI X 1 10 1 11 2 7 133 MHz 3 21 5 9 133 MHz capable bit 4...

Страница 162: ...5 diagnostic read write data 4 34 expansion ROM base address 4 14 header type 4 8 host diagnostic 4 32 host interrupt mask 2 16 3 8 3 9 4 37 host interrupt status 4 36 I O base address 4 9 interrupt l...

Страница 163: ...channel module 2 5 2 6 CLK 3 10 clock 3 10 core 2 6 CRC 2 22 datapath engine 2 6 domain validation 2 22 driver signals 5 3 DT clocking 1 2 2 18 dual channel 3 21 functions 2 15 information unit trans...

Страница 164: ...E 3 6 GNT 3 7 GPIO 7 0 3 19 ground 3 20 HB_LED 3 19 IDDTN 3 18 IDSEL 3 6 INTA 3 8 INTB 3 8 IOPD_GNT 3 16 IRDY 3 6 MAD 15 0 3 15 3 21 MADP 1 0 3 15 3 21 MCLK 3 14 MOE 3 15 NC 3 20 PAR 3 5 PAR64 3 5 PCI...

Страница 165: ...27 SREQ 5 3 SRST 5 3 SSEL 5 3 status IOP doorbell bit 4 36 register 4 5 4 26 STOP 3 6 5 5 stress ratings 5 2 subsystem ID 2 27 2 28 3 22 3 23 4 14 subsystem ID register 4 13 subsystem vendor ID 2 27...

Страница 166: ...l description 2 18 information unit 2 21 ISI 1 7 2 19 paced transfers 2 19 packetized transfers 2 21 parallel protocol request 2 18 2 22 PPR 2 18 precompensation 2 20 QAS 2 21 quick arbitration and se...

Страница 167: ...n this document Please copy the following page add your comments and fax it to us at the number shown If appropriate please also fax copies of any marked up pages from this document Important Please i...

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Страница 169: ...You can find a current list of our U S distributors international distributors and sales offices and design resource centers on our web site at http www lsilogic com contacts index html...

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