LSI LSI53C1030, Техническое руководство

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4-38 PCI Host Register Description
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Doorbell Interrupt Mask 0
Setting this bit masks System Doorbell interrupts and pre-
vents the assertion of a PCI interrupt for all System Door-
bell interrupt conditions.
Register: 0x40
Request FIFO
Read/Write
The Request FIFO provides Request Free Message Frame Addresses
(MFAs) to the host system on reads and accepts Request Post MFAs
from the host system on writes. There is one Request FIFO register that
is visible to both PCI functions. The two PCI functions physically share
this register.
Request FIFO
[
31:0]
For reads, the Request Free MFA is empty and this reg-
ister contains 0xFFFFFFFF. For writes, the register con-
tains the Request Post MFA.
Register: 0x44
Reply FIFO
Read/Write
The Reply FIFO provides Reply Post MFAs to the host system on reads
and accepts Reply Free MFAs from the host system on writes. There is
a unique Reply FIFO register for each PCI function.
Reply FIFO [31:0]
For reads, the Request Free MFA is empty and this reg-
ister contains 0xFFFFFFFF. For writes, the register con-
tains the Reply Free MFA.
31 0
Request FIFO
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
31 0
Reply FIFO
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1